參數(shù)資料
型號(hào): DAC1627D1G25HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 16-bit DAC, up to 1.25 Gsps; 2x 4x and 8x interpolating
封裝: DAC1627D1G25HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;
文件頁數(shù): 69/69頁
文件大?。?/td> 1677K
代理商: DAC1627D1G25HN
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 April 2011
Document identifier: DAC1627D1G25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.2.1
10.2.2
10.3
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.5
10.5.1
10.5.2
10.6
10.7
10.7.1
10.7.2
10.7.3
10.8
10.9
10.9.1
10.9.2
10.9.3
10.9.4
10.10
10.11
10.12
10.12.1
10.12.2
10.13
10.14
10.15
10.16
10.16.1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal characteristics . . . . . . . . . . . . . . . . . . 7
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Application information. . . . . . . . . . . . . . . . . . 12
General description . . . . . . . . . . . . . . . . . . . . 12
Serial Peripheral Interface (SPI). . . . . . . . . . . 13
Protocol description . . . . . . . . . . . . . . . . . . . . 13
SPI timing description. . . . . . . . . . . . . . . . . . . 14
Power-on sequence . . . . . . . . . . . . . . . . . . . . 14
LVDS Data Input Format (DIF) block . . . . . . . 15
Input port polarity . . . . . . . . . . . . . . . . . . . . . . 15
Input port mapping . . . . . . . . . . . . . . . . . . . . . 16
Input port swapping . . . . . . . . . . . . . . . . . . . . 16
Input port formatting . . . . . . . . . . . . . . . . . . . . 17
Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
LVDS DDR clock. . . . . . . . . . . . . . . . . . . . . . . 18
DAC core clock. . . . . . . . . . . . . . . . . . . . . . . . 18
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating modes . . . . . . . . . . . . . . . . . . . . . . 21
CDI mode 0 (x2 interpolation). . . . . . . . . . . . . 22
CDI mode 1 (x4 interpolation). . . . . . . . . . . . . 22
CDI mode 2 (x8 interpolation). . . . . . . . . . . . . 23
FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Single SideBand Modulator (SSBM). . . . . . . . 25
NCO in 40 bits . . . . . . . . . . . . . . . . . . . . . . . . 25
NCO low power . . . . . . . . . . . . . . . . . . . . . . . 26
Complex modulator . . . . . . . . . . . . . . . . . . . . 26
Minus 3dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Inverse sinx / x . . . . . . . . . . . . . . . . . . . . . . . . 27
DAC transfer function . . . . . . . . . . . . . . . . . . . 27
Full-scale current . . . . . . . . . . . . . . . . . . . . . . 28
Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Full-scale current adjustment . . . . . . . . . . . . . 28
Digital offset adjustment . . . . . . . . . . . . . . . . . 29
Analog output . . . . . . . . . . . . . . . . . . . . . . . . . 30
Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 31
Output configuration . . . . . . . . . . . . . . . . . . . . 32
Basic output configuration . . . . . . . . . . . . . . . 32
10.16.2
10.16.3
10.16.4
10.17
10.17.1
10.18
10.18.1
10.18.2
10.18.3
10.18.4
10.18.5
10.18.6
10.18.7
11
12
13
13.1
13.2
14
15
15.1
15.2
15.3
15.4
16
17
18
IQ-modulator - BGX7100 interface . . . . . . . . 33
IQ-modulator - DC interface. . . . . . . . . . . . . . 33
IQ-modulator - AC interface. . . . . . . . . . . . . . 36
Design recommendations . . . . . . . . . . . . . . . 36
Power and grounding. . . . . . . . . . . . . . . . . . . 36
Configuration interface. . . . . . . . . . . . . . . . . . 37
Register description. . . . . . . . . . . . . . . . . . . . 37
Page 0 register allocation map . . . . . . . . . . . 38
Page 0 bit definition detailed description . . . . 40
Page 1 allocation map . . . . . . . . . . . . . . . . . . 46
Page 1 bit definition detailed description . . . . 48
Page A register allocation map . . . . . . . . . . . 54
Page A bit definition detailed description. . . . 56
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 61
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 62
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Static parameters. . . . . . . . . . . . . . . . . . . . . . 63
Dynamic parameters . . . . . . . . . . . . . . . . . . . 63
Revision history . . . . . . . . . . . . . . . . . . . . . . . 64
Legal information . . . . . . . . . . . . . . . . . . . . . . 65
Data sheet status. . . . . . . . . . . . . . . . . . . . . . 65
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Contact information . . . . . . . . . . . . . . . . . . . . 66
Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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