參數資料
| 型號： | CS8952-IQZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數： | 40/81頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX 100/10 PHY 100TQFP |
| 標準包裝： | 90 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 759 (CN2011-ZH PDF) |
| 其它名稱： | 598-1208 |
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CS8952
CrystalLAN 100BASE-X and 10BASE-T Transceiver
45
DS206F1
8
Remote Loopback
Fault
Read Only
0
When set, this bit indicates that the Elastic Buffer has
detected an over-run or an under-run condition. In
any case, the frame generating this fault will be ter-
minated.
This should never happen since the depth of the
elastic buffer (10 bits) is greater than twice the maxi-
mum number of bit times the receive and transmit
clocks may slip during a maximum length packet
assuming clock frequency tolerances of 100 ppm or
less.
7
Reset Complete
Read Only
0
When set, this bit indicates that the internal analog
calibration cycle has completed, and all analog and
digital circuitry is ready for normal operation.
6
Jabber Detect
Read Only
0
In 10BASE-T mode, if the last transmission is longer
than 105 ms, then the packet output is terminated by
the jabber logic and this bit is set.
This bit is implemented with a latching function so
that the occurrence of a jabber condition causes it to
become set until it is cleared by a read to this regis-
ter, a read to the Basic Mode Status Register
(address 01h), or a reset.
No jabber detect function has been defined for
100BASE-TX.
This bit is the same as in the Basic Mode Status Reg-
ister (address 01h).
5
Auto-Neg Complete Read Only
0
This bit is set when the auto-negotiation process has
completed. This is an indication that the Auto-Negoti-
ation Advertisement Register (address 04h), the
Auto-Negotiation Link Partner Ability Register
(address 05h), and the Auto-Negotiation Expansion
Register (address 06h) are valid.
This bit is the same as in the Basic Mode Status Reg-
ister (address 01h).
4
Parallel Detection
Fault
Read Only
0
When set, this bit indicates an error condition in
which auto-negotiation has detected that unstable
10BASE-T or 100BASE-TX link signalling was
received. This bit is self-clearing.
This bit is the same as in the Auto-Negotiation
Expansion Register (address 06h)
3
Parallel Fail
Read Only
0
When set, this bit indicates that a parallel detection
has occurred for a technology that is not currently
advertised by the local device.
BIT
NAME
TYPE
RESET
DESCRIPTION
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CS8952-IQZR | 功能描述:以太網 IC IC 100BASE-TX and 10BASE-T Transceiver RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數量:2 數據速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| CS8952T | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-CQ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-IQ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-IQR | 制造商:Cirrus Logic 功能描述:ETHERNET TXRX SGL CHIP 1-PORT 5V 10MBPS/100MBPS 100TQFP - Tape and Reel |
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