參數(shù)資料
型號(hào): CS8952-IQZ
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 28/81頁(yè)
文件大?。?/td> 0K
描述: IC TXRX 100/10 PHY 100TQFP
標(biāo)準(zhǔn)包裝: 90
類型: 收發(fā)器
規(guī)程: MII
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 759 (CN2011-ZH PDF)
其它名稱: 598-1208
CS8952
CrystalLAN 100BASE-X and 10BASE-T Transceiver
34
DS206F1
3
Auto-Neg Ability
Read Only
1
This bit indicates that the CS8952 has auto-negotia-
tion capability. Therefore this bit will always read
back a value of 1.
2
Link Status
Read Only
0
When set, this bit indicates that a valid link has been
established. Upon a link failure, this bit is cleared and
latched. It will remain cleared until this register is
read.
1
Jabber Detect
Read Only
0
In 10BASE-T mode, if the last transmission is longer
than 105 ms, then the packet output is terminated by
the jabber logic and this bit is set. If JabberiE (Inter-
rupt Mask Register (address 10h), bit 3) is set, an MII
Interrupt will be generated.
This bit is implemented with a latching function so
that the occurrence of a jabber condition causes it to
become set until it is cleared by a read to this regis-
ter, a read to the Interrupt Status Register (address
11h), or a reset.
No jabber detect function has been defined for
100BASE-TX.
0
Extended Capability Read Only
1
This bit indicates that an extended register set may
be accessed (registers beyond address 01h). This bit
always reads back a value of 1.
BIT
NAME
TYPE
RESET
DESCRIPTION
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