參數(shù)資料
型號(hào)： CS61584A-IQ3Z
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 22/47頁(yè)
文件大?。?/td> 0K
描述： IC LINE INTERFACE T1/E1 64LQFP
標(biāo)準(zhǔn)包裝： 160
接口： 并行/串行
電源電壓： 3.3V，5V
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
安裝類型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 759 (CN2011-ZH PDF)
其它名稱： 598-1713
CS61584A
DS261PP5
29
DS261PP5
tude information written for phases 13 and 14 of
each UI is ignored. Examples of arbitrary wave-
forms are illustrated in Figure 19.
The amplitude of each phase segment is described
by a 7-bit, 2’s complement number (bit 8 is ig-
nored). A positive value describes pulse amplitude
and a negative value describes pulse undershoot.
For DSX-1 applications with CON[3:0] = 1010, the
typical output voltage step is 73 mV/LSB across
the secondary (line side) of the transformer. For
DS1 applications with CON[3:0] = 1011, the typi-
cal output voltage step is 52 mV/LSB across the
transformer secondary. For E1 75
coaxial appli-
cations with CON[3:0] = 1000, the typical output
voltage step is 43 mV/LSB. For E1 120
twisted-
pair applications with CON[3:0] = 1001, the typi-
cal output voltage step is 52 mV/LSB.
The full scale positive value is 0x3F and the full
scale negative value is 0x40. It is recommended
that the output voltage across the secondary of the
transformer (line interface side) be limited to
4.4 Vpk. At higher output voltages, the transmitter
may not be able to drive the requested voltage
based on the current operating conditions.
Because the transmitter drives either a mark or a
space to the line interface every UI, the phase am-
plitude information defined in UI2 and UI3 is add-
ed to the symbols transmitted at TTIP and TRING
in those intervals. Therefore, a mark defined only
for UI1 will be output exactly as programmed if an-
other mark is transmitted in the next two UI. How-
ever, a mark defined over UI1 and UI2 with an
extended return-to-zero "tail" will cause the lead-
ing edge of a mark transmitted in the next UI to rise
or fall more quickly. This is illustrated in Figure 20.
If the hexadecimal sum of the phase amplitudes ex-
ceeds the full scale values, the sum is replaced by
the full scale value and the Latched-Overflow bit is
set in the Status register.
E1 Arbitrary Waveform Example
DSX-1 (54% duty cycle) Arbitrary Waveform Example
DS-1 (50% duty cycle) Arbitrary Waveform Example
Figure 19. Phase Definition of Arbitrary Waveforms
Figure 20. Example of Summing of Waveforms
CS61584A
DS261F1
29
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參數(shù)描述
CS61584A-IQ3ZR 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
CS61584A-IQ5 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
CS61584A-IQ5Z 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
CS61584A-IQ5ZR 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
CS61584-IL3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Line Interface
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