參數(shù)資料
型號： CS61584A-IQ3Z
廠商： Cirrus Logic Inc
文件頁數(shù)： 18/47頁
文件大?。?/td> 0K
描述： IC LINE INTERFACE T1/E1 64LQFP
標準包裝： 160
接口： 并行/串行
電源電壓： 3.3V，5V
封裝/外殼： 64-LQFP
供應商設備封裝： 64-LQFP（10x10）
包裝： 托盤
安裝類型： 表面貼裝
產(chǎn)品目錄頁面： 759 (CN2011-ZH PDF)
其它名稱： 598-1713
CS61584A
DS261PP5
25
DS261PP5
Latched-AIS: Set high on the rising edge of the
alarm indication signal condition. Reading the Sta-
tus register clears the Latched-AIS bit and deacti-
vates the INT pin. Refer to the timing diagram in
Figure 18.
Latched-BPV: Indicates a bipolar violation has
been received since the last read of the Status reg-
ister. Reading the Status register clears the
Latched-BPV bit and deactivates the INT pin. This
bit is set only when the line code decoder is enabled
in the Control A register.
Latched-Overflow: Indicates a waveform generat-
ed using the Arbitrary Waveform register has ex-
ceeded full scale since the last read of the Status
register. Reading the Status register clears the
Latched-Overflow bit and deactivates the INT pin.
Latched-Reset: Indicates a reset event (power-up or
RESET pin) has occurred since the last read of the
Status register. Reading the Status register clears
the Latched-Reset bit and deactivates the INT pin.
This bit is not maskable.
Latched-CLKLOST: Set high when TCLK or REF-
CLK are absent. Reading the Status register clears
the Latched-CLKLOST bit and deactivates the INT
pin.
Interrupt: Indicates a change in the Status register
since the last read. Reading the Status register
clears the Interrupt bit and deactivates the INT pin.
9.1.2
Mask Registers
The Mask registers are read-write registers and are
shown in Table 6. The Mask registers disables the
interrupts in the corresponding Status register on a
per-bit basis. Masking a Status register bit forces it
to remain at zero and prevents the INT pin from ac-
tivating on the condition.
Mask Register (Channel 1)
Serial Port Address: 0x12; Parallel Port Address: 0xY2
Bit
Description
Definition
Reset
Value
10
7
Mask LOS1
Mask Interrupt
Enable Interrupt
0
6
Mask Latched-LOS1
Mask Interrupt
Enable Interrupt
0
5
Mask AIS1
Mask Interrupt
Enable Interrupt
0
4
Mask Latched-AIS1
Mask Interrupt
Enable Interrupt
0
3
Mask Latched-BPV1
Mask Interrupt
Enable Interrupt
0
2
Mask Latched-Overflow1
Mask Interrupt
Enable Interrupt
0
1
Automatic All Ones, AAO
Ones at RPOS/NEG on LOS
Zeros at RPOS/NEG on LOS
0
Mask Interrupt1
Mask Interrupt
Enable Interrupt
0
Mask Register (Channel 2)
Serial Port Address: 0x13; Parallel Port Address: 0xY3
Bit
Description
Definition
Reset
Value
10
7
Mask LOS2
Mask Interrupt
Enable Interrupt
0
6
Mask Latched-LOS2
Mask Interrupt
Enable Interrupt
0
5
Mask AIS2
Mask Interrupt
Enable Interrupt
0
4
Mask Latched-AIS2
Mask Interrupt
Enable Interrupt
0
3
Mask Latched-BPV2
Mask Interrupt
Enable Interrupt
0
2
Mask Latched-Overflow2
Mask Interrupt
Enable Interrupt
0
1
Mask Latched-CLKLOST
Mask Interrupt
Enable Interrupt
0
Mask Interrupt2
Mask Interrupt
Enable Interrupt
0
Table 6. Mask Registers
CS61584A
DS261F1
25
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相關代理商/技術參數(shù)
參數(shù)描述
CS61584A-IQ3ZR 功能描述:網(wǎng)絡控制器與處理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
CS61584A-IQ5 功能描述:網(wǎng)絡控制器與處理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
CS61584A-IQ5Z 功能描述:網(wǎng)絡控制器與處理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
CS61584A-IQ5ZR 功能描述:網(wǎng)絡控制器與處理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
CS61584-IL3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Line Interface
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