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| 型號(hào)： | CS61584A-IQ3Z |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 19/47頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE INTERFACE T1/E1 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 接口： | 并行/串行 |
| 電源電壓： | 3.3V，5V |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤(pán) |
| 安裝類(lèi)型： | 表面貼裝 |
| 產(chǎn)品目錄頁(yè)面： | 759 (CN2011-ZH PDF) |
| 其它名稱(chēng)： | 598-1713 |
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CS61584A
26
DS261PP5
AAO: The Automatic All-Ones (AAO) bit in the
Mask Register (Channel 1, bit 1) causes an un-
framed all-ones pattern to be output at the RPOS
and RNEG (or RDATA) pins when the receiver is
in a loss of signal (LOS) condition.
9.1.3
Control A Registers
The Control A registers are read-write registers and
are shown in Table 7. The Control A registers se-
lect device configuration and power down control.
CLKE: Establishes the edge of the of RCLK that
RPOS and RNEG (or RDATA) are valid.
PD: Controls per channel power down.
ATTEN0 and ATTEN1: Controls the jitter attenu-
ator location and -3 dB knee frequency (See Jitter
Attenuator section).
CODER: Controls the coder mode function. The
TPOS, TNEG, RPOS, and RNEG pins are active
when the transparent mode is enabled. The TDA-
TA, RDATA, AIS, and BPV pins are active when
the coder mode is enabled.
AMI-T: Controls the line encoder in the transmit
direction. The selection of B8ZS or HDB3 is deter-
mined by the CON[3:0] bits (See the Transmitter
section).
AMI-R: Controls the line decoder in the receive di-
rection. The selection of B8ZS or HDB3 is deter-
mined by the CON[3:0] bits (See the Transmitter
section).
EXZ: Controls the automatic detection of excessive
zeros on the BPV pin according to ANSI T1.231
when coder mode is enabled (CODERx = 1).
Control A Register (Channel 1)
Serial Port Address: 0x14; Parallel Port Address: 0xY4
Bit
Description
Definition
Reset
Value
10
7
CLKE
RPOS/RNEG (or RDATA) valid on
falling edge of RCLK
RPOS/RNEG (or RDATA) valid on
rising edge of RCLK
0
6
PD1
Power down channel
Power up channel
0
5
ATTEN01
Jitter attenuator location
(See Jitter Attenuator section)
0
4ATTEN11
0
3
CODER1
Coder mode enabled
Transparent mode enabled
0
2
AMI-T1
AMI encoder enabled
B8ZS/HDB3 encoder enabled
0
1
AMI-R1
AMI decoder enabled
B8ZS/HDB3 decoder enabled
0
Factory Test
Test
Normal operation
0
Control A Register (Channel 2)
Serial Port Address: 0x15; Parallel Port Address: 0xY5
Bit
Description
Definition
Reset
Value
10
7
EXZ
Excessive zeros detection for both
channels enabled
Excessive zeros detection for both
channels disabled
0
6
PD2
Power down channel
Power up channel
0
5
ATTEN02
Jitter attenuator location
(See Jitter Attenuator section)
0
4ATTEN12
0
3
CODER2
Coder mode enabled
Transparent mode enabled
0
2
AMI-T2
AMI encoder enabled
B8ZS/HDB3 encoder enabled
0
1
AMI-R2
AMI decoder enabled
B8ZS/HDB3 decoder enabled
0
Factory Test
Test
Normal operation
0
Table 7. Control A Registers
CS61584A
26
DS261F1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS61584A-IQ3ZR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CS61584A-IQ5 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CS61584A-IQ5Z | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CS61584A-IQ5ZR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| CS61584-IL3 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Line Interface |
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