參數(shù)資料
型號(hào)： CH7301A
廠商： Electronic Theatre Controls, Inc.
英文描述： Chrontel CH7301 DVI Output Device
中文描述： 昆泰CH7301 DVI輸出設(shè)備
文件頁(yè)數(shù)： 4/30頁(yè)
文件大小： 485K
代理商： CH7301A
CHRONTEL
Table 1: Pin Description
CH7301A
4
201-0000-036 Rev 1.1, 3/20/2000
64-Pin
LQFP
22, 21
# Pins
Type
Symbol
Description
2
Out
TDC0,
TDC0*
TMDS
TM
Data Channel 0 Outputs
These pins provide the TMDS
TM
differential outputs for data
channel 0 (blue).
TMDS
TM
Data Channel 1 Outputs
These pins provide the TMDS
TM
differential outputs for data
channel 1 (green).
TMDS
TM
Data Channel 2 Outputs
25, 24
2
Out
TDC1,
TDC1*
28, 27
2
Out
TDC2,
TDC2*
These pins provide the TMDS
TM
differential outputs for data
channel 2 (red).
TMDS
TM
Link Clock Outputs
These pins provide the differential clock output for the
TMDS
TM
interface corresponding to data on the TDC[0:2]
outputs.
Current Set Resistor Input
This pin sets the DAC current. A 140 ohm resistor should be
connected between this pin and GND (DAC ground) using
short and wide traces.
Green Output
Red Output
Blue Output
No Connect
DVI Link Detect Output
This pin provides an open drain output which pulls low when a
termination change has been detected on the HPDET input.
The output is released through IIC control.
Buffered Clock Output
This output pin provides a buffered clock output, driven by the
DVDD supply. The output clock can be selected using the BCO
register.
Composite / Horizontal Sync Output
This pin is only for use with the TV-Out function.
D[11] - D[0]
Data[11] through Data[0] Inputs
These pins accept the 12 data inputs from a digital video
port of a graphics controller. The levels are 0 to DVDDV,
and the VREF signal is used as the threshold level.
XCLK,
External Clock Inputs
These inputs form a differential clock signal input to the
CH7301 for use with the H, V, DE and D[11:0] data. If
differential clocks are not available, the XCLK* input
should be connected to VREF.
30, 31
2
Out
TLC,
TLC*
35
1
In
ISET
37
38
39
43
46
1
1
1
1
1
Out
Out
Out
G
R
B
NC
TLDET*
Out
47
1
Out
BCO
48
1
Out
C/H SYNC
50 – 55,
58 – 63
12
In
57, 56
2
In
XCLK*
The output clocks from this pad cell are able to have their
polarities reversed under the control of the MCP bit.
Digital Supply Voltage (3.3V)
Digital Ground
I/O Supply Voltage (3.3V - 1.1V)
DVI Transmitter Supply Voltage (3.3V)
DVI Transmitter Ground
PLL Supply Voltage (3.3V)
PLL Ground
DAC Supply Voltage (3.3V)
DAC Ground
1, 12, 49
6, 11, 64
45
23, 29
20, 26, 32
18, 44
16, 17, 41,42 4
33
34, 36, 40
3
3
1
2
3
2
Power
Power
Power
Power
Power
Power
Power
Power
Power
DVDD
DGND
DVDDV
TVDD
TGND
AVDD
AGND
VDD
GND
1
3
相關(guān)PDF資料
PDF描述
CH7301A-T Chrontel CH7301 DVI Output Device
CH7301A-T-A Chrontel CH7301 DVI Output Device
CH7301A-T-B Chrontel CH7301 DVI Output Device
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CHB-02A Surface Mountable Sound Generators CHB Series
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CH7301A-T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7301 DVI Output Device
CH7301A-T-A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7301 DVI Output Device
CH7301A-T-B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7301 DVI Output Device
CH7303 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7303 HDTV / DVI Encoder
CH7317A-TF 制造商:CHRONTEL 功能描述:SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQFP64
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