參數(shù)資料
型號(hào): CH7301A
廠商: Electronic Theatre Controls, Inc.
英文描述: Chrontel CH7301 DVI Output Device
中文描述: 昆泰CH7301 DVI輸出設(shè)備
文件頁(yè)數(shù): 16/30頁(yè)
文件大小: 485K
代理商: CH7301A
CHRONTEL
Transfer Protocols
(continued)
CH7301A
16
201-0000-036 Rev 1.1, 3/20/2000
AAR[6:0]
Specifies the Address of the Register to be Accessed.
This register address is loaded into the Address Register of the CH7301. The R/W access, which
follows, is directed to the register specified by the content stored in the Address Register.
The following two sections describe the operation of the serial interface for the four combinations of R/W = 0,1 and
AutoInc and alternating operation.
CH7301 Write Cycle Protocols (R/W = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the master-
transmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slave-
receiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the
HIGH period of the clock pulse. The CH7301 always acknowledges for writes (see
Figure 9
). Note that the
resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.
Figure 9: Acknowledge on the Bus
Figure 10
shows two consecutive alternating write cycles. The byte of information, following the Register Address
Byte (RAB), is the data to be written into the register specified by AR[6:0]. If AutoInc = 0, then another RAB is
expected from the master device, followed by another data byte, and so on.
Note:
The acknowledge is from the CH7301 (slave).
Figure 10: Alternating Write Cycles
SC from
Master
SD Data Output
By the CH7301
Start
Condition
2
SD Data Output
By Master-Transmitter
1
8
9
not acknowledge
acknowledge
clock pulse for
acknowledgment
SD
SC
1 - 8
RAB
9
ACK
Condition
Start
Condition
Stop
1 - 7
Device ID
8
R/W*
9
ACK
CH7301
acknowledge
CH7301
acknowledge
1 - 8
RAB
9
ACK
CH7301
acknowledge
1 - 8
Data
9
ACK
I
2
C
1 - 8
Data
9
ACK
CH7301
acknowledge
CH7301
acknowledge
相關(guān)PDF資料
PDF描述
CH7301A-T Chrontel CH7301 DVI Output Device
CH7301A-T-A Chrontel CH7301 DVI Output Device
CH7301A-T-B Chrontel CH7301 DVI Output Device
CHB-02 Surface Mountable Sound Generators CHB Series
CHB-02A Surface Mountable Sound Generators CHB Series
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CH7301A-T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7301 DVI Output Device
CH7301A-T-A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7301 DVI Output Device
CH7301A-T-B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7301 DVI Output Device
CH7303 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7303 HDTV / DVI Encoder
CH7317A-TF 制造商:CHRONTEL 功能描述:SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQFP64