參數(shù)資料
型號: CH7301A
廠商: Electronic Theatre Controls, Inc.
英文描述: Chrontel CH7301 DVI Output Device
中文描述: 昆泰CH7301 DVI輸出設(shè)備
文件頁數(shù): 15/30頁
文件大?。?/td> 485K
代理商: CH7301A
201-0000-036 Rev 1.1, 3/20/2000
15
CHRONTEL
Transfer Protocol
CH7301A
Both read and write cycles can be executed in “Alternating” and “Auto-increment” modes. Alternating mode
expects a register address prior to each read or write from that location (i.e., transfers alternate between address and
data). Auto-increment mode allows you to establish the initial register location, then automatically increments the
register address after each subsequent data access (i.e., transfers will be address, data...). A basic serial port transfer
protocol is shown in
Figure 8
and described below.
Figure 8: Serial Port Transfer Protocol
1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the
“START” condition. Transitions of address and data bits can only occur while SC is low.
2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the
“STOP” condition.
3. Upon receiving the first START condition, the CH7301 expects a Device Address Byte (DAB) from the
master device. The value of the device address is shown in the DAB data format below.
4. After the DAB is received, the CH7301 expects a Register Address Byte (RAB) from the master. The
format of the RAB is shown in the RAB data format below (note that B7 is not used).
Device Address Byte (DAB)
R/W
Read/Write Indicator
“0”:
master device will write to the CH7301 at the register location specified by the address
AR[6:0]
“1”:
master device will read from the CH7301 at the register location specified by the
address AR[6:0].
Register Address Byte (RAB)
B7
B6
B5
B4
B3
B2
B1
B0
1
1
1
0
1
0
1
R/W
B7
B6
B5
B4
B3
B2
B1
B0
1
AR[6]
AR[5]
AR[4]
AR[3]
AR[2]
AR[1]
AR[0]
SD
SC
1 - 8
9
Data
1
ACK
acCH7301
Condition
Start
Condition
Stop
CH7301
acknowledge
1 - 8
Data n
9
acCH7301
Device ID
8
R/W*
9
ACK
I
2
C
CH7301
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