
201-0000-036 Rev 1.1, 3/20/2000
13
CHRONTEL
Register Control
The CH7301 is controlled via an IIC control port. The IIC bus uses only the SC clock to latch data into
registers, and does not use any internally generated clocks so that the device can be written to in all power
down modes. The device retains all register states
CH7301A
The CH7301 contains a total of 37 registers for user control.
Control Registers Map
The controls are listed below, divided into three sections: general controls, input / output controls and DVI
controls. A register map and register description follows.
GENERAL CONTROLS
ResetIB
ResetDB
PD[6:0]
VID[7:0]
DID[7:0]
TSTP[1:0]
Software IIC reset
Software datapath reset
Power down controls (DVIP, DVIL, , DACPD[2:0], Full, Partial)
Version ID register
Device ID register
Enable/select test pattern generation (color bar, ramp)
INPUT/OUTPUT CONTROLS
XCM
XCMD[7:0]
MCP
HPIE, HPIE2
HPIR
IDF[2:0]
IBS
TERM[5:0]
BCOEN
BCO[2:0]
BCOP
GPIOL[1:0]
GOENB[1:0]
SYNCO[1:0]
DACG[1:0]
DACBP
XCLK 1X, 2X select
Delay adjust between XCLK and D[11:0]
XCLK polarity control
Hot plug detect interrupt enable
Hot plug detect interrupt reset
Input data format
Input buffer select
Termination detect/check (DVI Link, DACT3, DACT2, DACT1, DACT0, SENSE)
Enable BCO Output
Select output signal for BCO pin
BCO polarity
Read or write level for GPIO pins
Direction control for GPIO pins
Enables/selects sync output for bypass modes
DAC gain control
DAC bypass
DVI CONTROLS
TPPD[2:0]
TPCP[1:0]
TPVT[5:0]
TPVCO[10:0]
TPLPF[3:0]
DVID[3:0]
DVII
CTL[3:0]
DVI PLL phase detector trim
DVI PLL charge pump trim
DVI PLL VDD trim
DVI PLL VCO trim
DVI PLL low pass filter
DVI transmitter drive strength
DVI output invert
DVI control inputs