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參數(shù)資料
| 型號(hào)： | CC113LRTKT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 無(wú)繩電話/電話 |
| 英文描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQCC20 |
| 封裝： | 4 X 4 MM, GREEN, PLASTIC, VQFN-20 |
| 文件頁(yè)數(shù)： | 60/75頁(yè) |
| 文件大?。?/td> | 1454K |
| 代理商： | CC113LRTKT |
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CC113L
SWRS108A
Page 63 of 68
26.2 Configuration Register Details - Registers that Loose Programming in SLEEP State
0x29: RESERVED
Bit
Field Name
Reset
R/W
Description
7:0
89 (0x59)
R/W
Use setting from SmartRF Studio [4]
0x2A: RESERVED
Bit
Field Name
Reset
R/W
Description
7:0
127 (0x7F)
R/W
Use setting from SmartRF Studio [4]
0x2B: RESERVED
Bit
Field Name
Reset
R/W
Description
7:0
63 (0x3F)
R/W
Use setting from SmartRF Studio [4]
0x2C: TEST2 - Various Test Settings
Bit
Field Name
Reset
R/W
Description
7:0
TEST2[7:0]
136 (0x88)
R/W
Use setting from SmartRF Studio [4]
This register will be forced to 0x88 or 0x81 when it wakes up from SLEEP
mode, depending on the configuration of FIFOTHR.ADC_RETENTION.
Note that the value read from this register when waking up from SLEEP
always is the reset value (0x88) regardless of the ADC_RETENTION
setting. The inverting of some of the bits due to the ADC_RETENTION
setting is only seen INTERNALLY in the analog part.
0x2D: TEST1 - Various Test Settings
Bit
Field Name
Reset
R/W
Description
7:0
TEST1[7:0]
49 (0x31)
R/W
Use setting from SmartRF Studio [4]
This register will be forced to 0x31 or 0x35 when it wakes up from SLEEP
mode, depending on the configuration of FIFOTHR.ADC_RETENTION.
Note that the value read from this register when waking up from SLEEP
always is the reset value (0x31) regardless of the ADC_RETENTION
setting. The inverting of some of the bits due to the ADC_RETENTION
setting is only seen INTERNALLY in the analog part.
0x2E: TEST0 - Various Test Settings
Bit
Field Name
Reset
R/W
Description
7:2
TEST0[7:2]
2 (000010)
R/W
Use setting from SmartRF Studio [4]
1
VCO_SEL_CAL_EN
1
R/W
Enable VCO selection calibration stage when 1
0
TEST0[0]
1
R/W
Use setting from SmartRF Studio [4]
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