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參數(shù)資料
| 型號： | CC113LRTKT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQCC20 |
| 封裝： | 4 X 4 MM, GREEN, PLASTIC, VQFN-20 |
| 文件頁數(shù)： | 35/75頁 |
| 文件大?。?/td> | 1454K |
| 代理商： | CC113LRTKT |
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CC113L
SWRS108A
Page 40 of 68
20 Frequency Programming
The frequency programming in
CC113L is
designed
to
minimize
the
programming
needed when changing frequency.
To set up a system with channel numbers, the
desired channel spacing is programmed with
the
and
MDMCFG1.CHANSPC_E registers. The channel
spacing registers are mantissa and exponent
respectively. The base or start frequency is set
by the 24 bit frequency word located in the
FREQ2, FREQ1, and FREQ0 registers. This
word will typically be set to the centre of the
lowest channel frequency that is to be used.
The desired channel number is programmed
with
the
8-bit
channel
number
register,
CHANNR.CHAN, which is multiplied by the
channel offset. The resultant carrier frequency
is given by:
))
2
)
_
256
((
(
2
_
16
E
CHANSPC
XOSC
carrier
M
CHANSPC
CHAN
FREQ
f
With a 26 MHz crystal the maximum channel
spacing is 405 kHz. To get e.g. 1 MHz channel
spacing, one solution is to use 333 kHz
channel spacing and select each third channel
in CHANNR.CHAN.
The preferred IF frequency is programmed
with the FSCTRL1.FREQ_IF register. The IF
frequency is given by:
IF
FREQ
f
XOSC
IF
_
2
10
If any frequency programming register is
altered when the frequency synthesizer is
running,
the
synthesizer
may
give
an
undesired response. Hence, the frequency
should only be updated when the radio is in
the IDLE state
21 VCO
The VCO is completely integrated on-chip.
21.1 VCO and PLL Self-Calibration
The VCO characteristics vary with temperature
and supply voltage changes as well as the
desired
operating
frequency.
In
order
to
ensure reliable operation, CC113L includes
frequency synthesizer self-calibration circuitry.
This calibration should be done regularly, and
must be performed after turning on power and
before using a new frequency (or channel).
The number of XOSC cycles for completing
the PLL calibration is given in Table 26 on
page 38.
The calibration can be initiated automatically
or
manually.
The
synthesizer
can
be
automatically
calibrated
each
time
the
synthesizer is turned on, or each time the
synthesizer is turned off automatically. This is
configured
with
the
register
setting.
In
manual
mode,
the
calibration
is
initiated
when
the
command strobe is activated in the IDLE
mode.
To check that the PLL is in lock, the user can
program
register
to
0x0A, and use the lock detector output
available on the GDOx pin as an interrupt for
the MCU (x = 0,1, or 2). A positive transition
on the GDOx pin means that the PLL is in
lock. As an alternative the user can read
register FSCAL1. The PLL is in lock if the
register content is different from 0x3F. Refer
For more robust operation, the source code
could include a check so that the PLL is re-
calibrated until PLL lock is achieved if the PLL
does not lock the first time.
22 Voltage Regulators
CC113L contains several on-chip linear voltage
regulators that generate the supply voltages
needed
by
low-voltage
modules.
These
voltage regulators are invisible to the user, and
can be viewed as integral parts of the various
modules. The user must however make sure
that
the
absolute
maximum
ratings
and
Note:
The
calibration
values
are
maintained
in
SLEEP
mode,
so
the
calibration is still valid after waking up from
SLEEP mode unless supply voltage or
temperature has changed significantly.
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