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參數(shù)資料
| 型號(hào)： | CC113LRTKT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQCC20 |
| 封裝： | 4 X 4 MM, GREEN, PLASTIC, VQFN-20 |
| 文件頁數(shù)： | 38/75頁 |
| 文件大?。?/td> | 1454K |
| 代理商： | CC113LRTKT |
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CC113L
SWRS108A
Page 43 of 68
24 Asynchronous and Synchronous Serial Operation
Several features and modes of operation have
been
included
in
the
CC113L to provide
backward compatibility with previous Chipcon
products and other existing RF communication
systems. For new systems, it is recommended
to use the built-in packet handling features, as
they can give more robust communication,
significantly offload the microcontroller, and
simplify software development.
24.1 Asynchronous Serial Operation
Asynchronous transfer is included in the
CC113L for backward compatibility with systems
that are already using the asynchronous data
transfer.
When asynchronous transfer is enabled, all
packet handling support is disabled and it is
not possible to use Manchester encoding.
Asynchronous serial mode is enabled by
setting PKTCTRL0.PKT_FORMAT to 3. Data
output can be on GDO0, GDO1, or GDO2.
This
is
set
by
the
fields.
In asynchronous serial mode no data decision
is done on-chip and the raw data is put on the
data output line. When using asynchronous
serial mode make sure the interfacing MCU
does proper oversampling and that it can
handle the jitter on the data output line. The
MCU should tolerate a jitter of ±1/8 of a bit
period as the data stream is time-discrete
using 8 samples per bit.
In asynchronous serial mode there will be
glitches of 37 - 38.5 ns duration (1/XOSC)
occurring
infrequently
and
with
random
periods. A simple RC filter can be added to the
data output line between CC113L and the MCU
to get rid of the 37 - 38.5 ns glitches if
considered a problem. The filter 3 dB cut-off
frequency needs to be high enough so that the
data is not filtered and at the same time low
enough to remove the glitch. As an example,
for 2.4 kBaud data rate a 1 k
resistor and
2.7 nF capacitor can be used. This gives a 3
dB cut-off frequency of 59 kHz.
24.2
Synchronous Serial Operation
Setting
to
1
enables synchronous serial mode. When using
this mode, sync detection should be disabled
together
with
CRC
calculation
and
Infinite
packet
length
mode
should
be
used
In
synchronous
serial
mode,
data
is
transferred on a two-wire serial interface. The
CC113L provides a clock that is used to sample
data on the data output line. The data output
pin can be any of the GDO pins. This is set by
the
fields. The RX latency is 9 bits.
The MCU must handle preamble and sync
word detection in software, together with CRC
calculation.
25 System Considerations and Guidelines
25.1 SRD Regulations
International regulations and national laws
regulate the use of radio receivers and
transmitters. Short Range Devices (SRDs) for
license free operation below 1 GHz are usually
operated in the 315 MHz, 433 MHz, 868 MHz
or 915 MHz frequency bands. The CC113L is
specifically designed for such use with its
300 - 348 MHz, 387 - 464 MHz, and
779 - 928 MHz operating ranges. The most
important regulations when using the CC113L in
the 315 MHz, 433 MHz, 868 MHz, or 915 MHz
frequency bands are EN 300 220 V2.3.1
(Europe) and FCC CFR47 part 15 (USA).
For compliance with modulation bandwidth
requirements under EN 300 220 V2.3.1 in the
863 to 870 MHz frequency range it
is
recommended to use a 26 MHz crystal for
frequencies below 869 MHz and a 27 MHz
crystal for frequencies above 869 MHz.
Please note that compliance with regulations
is
dependent
on
the
complete
system
performance. It is the customers responsibility
to ensure that the system complies with
regulations.
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