參數(shù)資料
型號(hào)： CC113LRTKT
廠商： TEXAS INSTRUMENTS INC
元件分類： 無(wú)繩電話/電話
英文描述： TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQCC20
封裝： 4 X 4 MM, GREEN, PLASTIC, VQFN-20
文件頁(yè)數(shù)： 24/75頁(yè)
文件大?。?/td> 1454K
代理商： CC113LRTKT
CC113L
SWRS108A
Page 30 of 68
15.3 Packet Handling
In RX mode, the demodulator and packet
handler will search for a valid sync word.
When found, the demodulator has obtained
both bit and byte synchronization and will
receive the first payload byte.
When variable packet length mode is enabled,
the first byte is the length byte. The packet
handler stores this value as the packet length
and receives the number of bytes indicated by
the length byte. If fixed packet length mode is
used, the packet handler will accept the
programmed number of bytes.
Next, the packet handler optionally checks the
address and only continues the reception if the
address matches. If automatic CRC check is
enabled, the packet handler computes CRC
and matches it with the appended CRC
checksum.
At the end of the payload, the packet handler
will optionally write two extra packet status
bytes (see Table 19 and Table 20) that contain
CRC status, link quality indication, and RSSI
value.
15.4 Packet Handling in Firmware
When implementing a packet oriented radio
protocol in firmware, the MCU needs to know
when
a
packet
has
been
received.
Additionally, for packets longer than 64 bytes,
the RX FIFO needs to be read while in RX
mode. This means that the MCU needs to
know the number of bytes that can be read
from the RX FIFO. There are two possible
solutions
to
get
the
necessary
status
information:
a) Interrupt Driven Solution
The GDO pins can be used to give an interrupt
when a sync word has been received or when
a complete packet has been received by
setting IOCFGx.GDOx_CFG=0x06. In addition,
there
are
two
configurations
for
the
IOCFGx.GDOx_CFG register that can be used
as an interrupt source to provide information
on how many bytes that are in the RX FIFO
and
more information.
b) SPI Polling
The PKTSTATUS register can be polled at a
given rate to get information about the current
GDO2 and GDO0 values respectively. The
RXBYTES register can be polled at a given rate
to get information about the number of bytes in
the RX FIFO. Alternatively, the number of
bytes in the RX FIFO can be read from the
chip status byte returned on the MISO line
each time a header byte, data byte, or
command strobe is sent on the SPI bus.
It is recommended to employ an interrupt
driven solution since high rate SPI polling
reduces the RX sensitivity. Furthermore, as
explained in Section 10.3 and the CC113L
Errata Notes [3], when using SPI polling, there
is a small, but finite, probability that a single
read
from
registers
and
RXBYTES is being corrupt. The same is the
case when reading the chip status byte.
16 Modulation Formats
CC113L supports amplitude, frequency, and
phase shift modulation formats. The desired
modulation
format
is
set
in
the
Optionally, if the data has been Manchester
coded on the transmitter side it can be
decoded by the demodulator. This option is
enabled
by
setting
16.1 Frequency Shift Keying
CC113L
supports
2-(G)FSK
and
4-FSK
modulation.
When
selecting
4-FSK,
the
preamble and sync word to be received needs
to be 2-FSK (see Figure 13).
When 2-FSK/GFSK/4-FSK modulation is used,
the DEVIATN register specifies the expected
frequency deviation of incoming signals in RX
and should be the same as the deviation of the
Note:
Manchester
encoding
is
not
supported at the same time as using 4-
FSK modulation
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