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| 型號： | BU-65170G1-290 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| 封裝： | CERAMIC PACKAGE-70 |
| 文件頁數(shù)： | 6/47頁 |
| 文件大?。?/td> | 1143K |
| 代理商： | BU-65170G1-290 |
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14
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
T-6/09-0
AUTOMATIC RETRIES
The BU-61580 BC implements automatic message retries. When
enabled, retries will occur, following response timeout or format
error conditions. As additional options, retries may be enabled
when the Message Error Status Word bit is set by a 1553A RT
or following a ”Status Set” condition. For a failed message, either
one or two message retries will occur, the bus channel (same or
alternate) is independently programmable for the first and sec-
ond retry attempts. Retries may be enabled or disabled on an
individual message basis.
BC INTERRUPTS
BC interrupts may be enabled by the Interrupt Mask Register for
Stack Rollover, Retry, End-of-Message (global), End-of-Message
(in conjunction with the BC Control Word for individual messag-
es), response timeout, message error, end of BC frame, and
Status Set conditions. The definition of “Status Set” is program-
mable on an individual message basis, by means of the BC
Control Word. This allows for masking (“care/don't care”) of the
individual RT Status Word bits.
REMOTE TERMINAL (RT) ARCHITECTURE
The RT protocol design of the BU-65170/61580 represents
DDC's fifth generation implementation of a 1553 RT. One of the
salient features of the ACE's RT architecture is its true multipro-
tocol functionality. This includes programmable options for sup-
port of MIL-STD-1553A, the various McAir protocols, and MIL-
STD-1553B Notice 2. The BU-65170/61580 RT response time is
2 to 5 s dead time (4 to 7 s per 1553B), providing compliance
to all the 1553 protocols. Additional multiprotocol features of the
BU-65170/61580 include options for full software control of RT
Status and Built-in-Test (BIT) words. Alternatively, for 1553B
applications, these words may be formulated in real time by the
BU-65170/61580 protocol logic.
The BU-65170/61580 RT protocol design implements all the
MIL-STD-1553B message formats and dual redundant mode
15
13
0
CURRENT
AREA B/A
CONFIGURATION
REGISTER 1
INITIAL STACK
POINTERS (NOTE)
INITIAL MESSAGE
COUNTERS (NOTE)
MESSAGE
COUNTERS
STACK
POINTERS
BLOCK STATUS WORD
TIME TAG WORD
MESSAGE
GAP TIME WORD
MESSAGE
BLOCK ADDR
DESCRIPTOR
STACKS
MESSAGE
BLOCKS
MESSAGE
BLOCK
MESSAGE
BLOCK
NOTE:
INITIAL STACK POINTERS AND INITIAL
MESSAGE COUNTERS USED ONLY IN
BC FRAME AUTO-REPEAT MODE.
FIGURE 3. BC MODE MEMORY MANAGEMENT
codes. This design is based largely on previous generation prod-
ucts that have passed SEAFAC testing for MIL-STD-1553B
compliance. The ACE RT performs comprehensive error check-
ing, word and format validation, and checks for various RT-to-RT
transfer errors. Other key features of the BU-65170/61580 RT
include a set of interrupt conditions, internal command illegaliza-
tion, and programmable busy by subaddress.
RT MEMORY ORGANIZATION
TABLE 26 illustrates a typical memory map for the BU-61580 in
RT mode. As in BC mode, the two Stack Pointers reside in fixed
locations in the shared RAM address space: address 0100 (hex)
for the Area A Stack Pointer and address 0104 for the Area B
Stack Pointer. Besides the Stack Pointer, for RT mode there are
several other areas of the ACE address space designated as
fixed locations. All RT modes of operation require the Area A and
Area B Lookup Tables. Also allocated are several fixed locations
for optional features: Command Illegalization Lookup Table,
Mode Code Selective Interrupt Table, Mode Code Data Table,
and Busy Bit Lookup Table. It should be noted that any unen-
abled optional fixed locations may be used for general purpose
storage (data blocks).
The RT Lookup tables, which provide a mechanism for mapping
data blocks for individual Tx/Rx/Bcst-subaddresses to areas in
the RAM, occupy address range locations are 0140 to 01BF for
Area A and 01C0 to 023F for Area B. The RT lookup tables
include Subaddress Control Words and the individual Data Block
Pointers. If used, address range 0300-03FF will be dedicated as
the illegalizing section of RAM. The actual Stack RAM area and
the individual data blocks may be located in any of the nonfixed
areas in the shared RAM address space.
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