參數(shù)資料
型號(hào)： BU-6486NEW
英文描述： MIL-STD-1553 Components |Mini-ACE? Mark3
中文描述： 符合MIL - STD - 1553模塊|迷你ACE論壇？ Mark3
文件頁(yè)數(shù)： 44/60頁(yè)
文件大?。?/td> 410K
代理商： BU-6486NEW
44
Data Device Corporation
www.ddc-web.com
BU-64743/64843/64863
C-03/03-300
SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS
+3.3V_Xcvr
10
+3.3V_Logic
30, 51, 69
Gnd_Xcvr
22, 79
Gnd_Logic
31, 50, 70
TABLE 47. POWER AND GROUND
BU-64743X0
BU-64843X0
BU-64863X0
SIGNAL NAME
BU-64743X8/X9
BU-64843X8/X9
BU-64863X8/X9
PIN
-
10, 30, 51, 69
-
22, 79, 31, 50, 70
PIN
Transceiver Power
Logic Power
Transceiver Ground
Logic Ground
DESCRIPTION
TXDATA_A (O)
3
TXDATA_A (O)
5
RXDATA_A (I)
8
RXDATA_A
(I, not enabled)*
4
TABLE 49. INTERFACE TO EXTERNAL TRANSCEIVER (BU-64XX3X0 TRANSCEIVERLESS VERSION)
BU-64743X0
BU-64843X0
BU-64863X0
SIGNAL NAME
PIN
Digital Manchester biphase transmit outputs, A bus
Digital Manchester biphase receive inputs, A bus
TXINH_A_OUT (O)
11
TXDATA_B (O)
15
TXDATA_B (O)
17
RXDATA_B (I)
21
Digital output to inhibit external transmitter, A bus
Digital Manchester biphase transmit outputs, B bus
Digital Manchester biphase receive inputs, B bus
RXDATA_B
(I, not enabled)*
16
TXINH_B_OUT (O)
9
Digital output to inhibit external transmitter, B bus
UPADDREN / NC
14
4K versions: UPADDREN / 64K versions: NC
For 4K RAM versions, this signal is always configured as UPADDREN.
This signal is used to control the function of the upper 4 address inputs (A15-A12). For these versions of
Mark3 if UPADDREN is connected to logic "1", then these four signals operate as address lines A15-A12. If
UPADDREN is connected to logic "0", then A15 and A14 function as CLK_SEL_1 and CLK_SEL_0 respec-
tively; A13 MUST be connected to +3.3V-LOGIC; and A12 functions as RTBOOT.
DESCRIPTION
TX/RX-A (I/O)
3
Analog Transmit/Receive Input/Outputs. Connect directly to 1553 isolation transformers.
TX/RX-A (I/O)
5
TX/RX-B (I/O)
15
TX/RX-B (I/O)
17
TABLE 48. 1553 ISOLATION TRANSFORMER (BU-64XX3X8/9 VERSIONS)
BU-64743X8/9
BU-64843X8/9
BU-64863X8/9
SIGNAL NAME
DESCRIPTION
PIN
*NOTE: Standard transceiverless parts have their receiver inputs internally strapped for single-ended operation.The RXDATAx_L
pins are connected to inputs that are not enabled. Contact the factory for a non-standard part that enables differential receive
inputs.
NOTE: Logic ground and transceiver ground
are not
tied together inside the package.
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