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參數(shù)資料
| 型號(hào)： | BU-6486NEW |
| 英文描述： | MIL-STD-1553 Components |Mini-ACE? Mark3 |
| 中文描述： | 符合MIL - STD - 1553模塊|迷你ACE論壇？ Mark3 |
| 文件頁數(shù)： | 15/60頁 |
| 文件大?。?/td> | 410K |
| 代理商： | BU-6486NEW |
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Data Device Corporation
www.ddc-web.com
BU-64743/64843/64863
C-03/03-300
vidual receive (broadcast) subaddresses, and the alternate (fully
software programmable) RT Status Word. For MT mode, use of
the Enhanced Mode enables the Selective Message Monitor, the
combined RT/Selective Monitor modes, and the monitor trigger-
ing capability.
RT/MONITOR DATA STACK ADDRESS REGISTER
The RT/Monitor Data Stack Address Register provides a
read/writable indication of the last data word stored for RT or
Monitor modes.
BC FRAME TIME REMAINING REGISTER
The BC Frame Time Remaining Register provides a read-only
indication of the time remaining in the current BC frame. In the
enhanced BC mode, this timer may be used for minor or major
frame control, or as a watchdog timer for the BC message
sequence control processor. The resolution of this register is
100 μs/LSB.
BC TIME REMAINING TO NEXT MESSAGE REGISTER
The BC Time Remaining to Next Message Register provides a
read-only indication of the time remaining before the start of the
next message in a BC frame. In the enhanced BC mode, this
timer may also be used for the BC message sequence control
processor's Delay (DLY) instruction, or for minor or major frame
control.The resolution of this register is 1 μs/LSB.
BC FRAME TIME/ RT LAST COMMAND /MT TRIGGER
WORD REGISTER
In BC mode, this register is used to program the BC frame time,
for use in the frame auto-repeat mode.The resolution of this reg-
ister is 100 μs/LS, with a range up to 6.55 seconds. In RT mode,
this register stores the current (or most previous) 1553
Command Word processed by the Mini-ACE Mark3 RT. In the
Word Monitor mode, this register is used to specify a 16-bit
Trigger (Command) Word. The Trigger Word may be used to
start or stop the monitor, or to generate interrupts.
BC INITIAL INSTRUCTION LIST POINTER REGISTER
The BC Initial Instruction List Pointer Register enables the host
to assign the starting address for the enhanced BC Instruction
List.
RT STATUS WORD REGISTER AND BIT WORD
REGISTERS
The RT Status Word Register and BIT Word Registers provide
read-only indications of the RT Status and BIT Words.
CONFIGURATION REGISTERS #6 AND #7:
Configuration Registers #6 and #7 are used to enable the Mini-
ACE Mark3 features that extend beyond the architecture of the
ACE/Mini-ACE (Plus). These include the Enhanced BC mode;
RT Global Circular Buffer (including buffer size); the RT/MT
Interrupt Status Queue, including valid/invalid message filtering;
enabling a software-assigned RT address; clock frequency
selection; a base address for the "non-data" portion of Mini-ACE
BC/RT COMMAND STACK REGISTER
The BC/RT Command Stack Register allows the host CPU to
determine the pointer location for the current or most recent
message.
BC INSTRUCTION LIST POINTER REGISTER
The BC Instruction List Pointer Register may be read to deter-
mine the current location of the Instruction List Pointer for the
Enhanced BC mode.
BC CONTROL WORD/RT SUBADDRESS CONTROL
WORD REGISTER
In BC mode, the BC Control Word/RT Subaddress Control Word
Register allows host access to the current word or most recent
BC Control Word. The BC Control Word contains bits that select
the active bus and message format, enable off-line self-test,
masking of Status Word bits, enable retries and interrupts, and
specify MIL-STD-1553A or -1553B error handling. In RT mode,
this register allows host access to the current or most recent
Subaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enable
interrupts for the current message.
TIME TAG REGISTER
The Time Tag Register maintains the value of a real-time clock.
The resolution of this register is programmable from among 2, 4,
8, 16, 32, and 64 μs/LSB. The Start-of-Message (SOM) and
End-of-Message (EOM) sequences in BC, RT, and Message
Monitor modes cause a write of the current value of the Time Tag
Register to the stack area of the RAM.
INTERRUPT STATUS REGISTERS #1 AND #2
Interrupt Status Registers #1 and #2 allow the host processor to
determine the cause of an interrupt request by means of one or
two read accesses. The interrupt events of the two Interrupt
Status Registers are mapped to correspond to the respective bit
positions in the two Interrupt Mask Registers. Interrupt Status
Register #2 contains an INTERRUPT CHAIN bit, used to indi-
cate an interrupt event from Interrupt Status Register #1.
CONFIGURATION REGISTERS #3, #4, AND #5
Configuration Registers #3, #4, and #5 are used to enable many
of the Mini-ACE Mark3’s advanced features that were imple-
mented by the prior generation products, the ACE and Mini-ACE
(Plus). For BC, RT, and MT modes, use of the Enhanced Mode
enables the various read-only bits in Configuration Register #1.
For BC mode, Enhanced Mode features include the expanded
BC Control Word and BC Block Status Word, additional Stop-On-
Error and Stop-On-Status Set functions, frame auto-repeat, pro-
grammable intermessage gap times, automatic retries, expand-
ed Status Word Masking, and the capability to generate inter-
rupts following the completion of any selected message. For RT
mode, the Enhanced Mode features include the expanded RT
Block Status Word, combined RT/Selective Message Monitor
mode, automatic setting of the TERMINAL FLAG Status Word bit
following a loop test failure; the double buffering scheme for indi-
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