- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369546 > BU-6486NEW MIL-STD-1553 Components |Mini-ACE? Mark3 PDF資料下載
參數(shù)資料
| 型號： | BU-6486NEW |
| 英文描述： | MIL-STD-1553 Components |Mini-ACE? Mark3 |
| 中文描述： | 符合MIL - STD - 1553模塊|迷你ACE論壇？ Mark3 |
| 文件頁數(shù)： | 38/60頁 |
| 文件大小： | 410K |
| 代理商： | BU-6486NEW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當(dāng)前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
38
Data Device Corporation
www.ddc-web.com
BU-64743/64843/64863
C-03/03-300
CLOCK IN
VALID
t7
t3
t8
t11
t13
t15
VALID
t10
t4
t9
t12
t19
VALID
t16
t17
SELECT
(Note 2,7)
(Note 2)
(Note 3,4,7)
(Note 4,5)
STRBD
MEM/REG
RD/WR
IOEN
(Note 2,6)
(Note 6)
(Note 6)
(Note 7,8,9)
READYD
A15-A0
D15-D0
t5
t1
t2
t6
t14
t18
FIGURE 13. CPU READING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)
NOTES:
1.
For the 16-bit buffered nonzero wait configuration, TRANSPARENT/BUFFERED must be connected to logic "0". ZERO_WAIT and DTREQ / 16/8
must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either +3.3 V or ground.
SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT STRBD is sampled low (satisfying t1)
and the Mark3’s protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer
cycle. After IOEN goes low, SELECT may be released high.
MEM/REG must be presented high for memory access, low for register access.
MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and
RD/WR become latched internally.
The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1." If POLARITY_SEL is connected to logic "0,"
RD/WR must be asserted low to read.
The timing for IOEN, READYD and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of IOEN, READYD, and D15-D0 is delayed
by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
The timing for A15-A0, MEM/REG and SELECT assumes that ADDR-LAT is connected to logic "1." Refer to Address Latch timing for additional
details.
The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0
become latched internally.
Setup time given for use in worst case timing calculations. None of the Mark3’s input signals are required to be synchronized to the system clock.
When SELECT and STRBD do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an additional clock cycle
will be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the Address (A15-A0).
When this occurs, the delay from IOEN falling to READYD falling (t11) increases by one clock cycle and the address hold time (t10) must be
increased be one clock cycle.
2.
3.
4.
5.
6.
7.
8.
9.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-6586NEW | MIL-STD-1553 Components |PCI Mini-ACE? Mark3 |
| BU-69200 | MIL-STD-1553 Components |ACE-Core |
| BU05MC | COMMON MODE CHOKE COILS (FOR DC AND SIGNAL LINES) SMD TYPE |
| BU105 | Transient Voltage Suppressor Diodes |
| BUY11 | Bipolar NPN Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-65-0 | 功能描述:測試電夾 ALLIGATOR CLIP BLK RoHS:否 制造商:Pomona Electronics 類型:Minigrabber clip 顏色:Black |
| BU65-0 | 制造商:MUELLER ELECTRIC CO. 功能描述: 制造商:Mueller Electric Company 功能描述: |
| BU-651-0 | 功能描述:測試電夾 Black Shrouded Small RoHS:否 制造商:Pomona Electronics 類型:Minigrabber clip 顏色:Black |
| BU-651-2 | 功能描述:測試電夾 Red Shrouded Small A RoHS:否 制造商:Pomona Electronics 類型:Minigrabber clip 顏色:Black |
| BU65170G0-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。