參數(shù)資料
型號: ATMEGA103-6AI
廠商: Atmel
文件頁數(shù): 94/141頁
文件大?。?/td> 0K
描述: IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 6MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
配用: ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
56
ATmega103(L)
0945I–AVR–02/07
1.
In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must
be written to WDE even though it is set to one before the disable operation starts.
2.
Within the next four clock cycles, write a logical “0” to WDE. This disables the
Watchdog.
Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
Time-out periods are shown in Table 21.
Note:
The frequency of the Watchdog Oscillator is voltage-dependent as shown in the Electri-
cal Characteristics section.
The WDR (Watchdog Reset) instruction should always be executed before the Watchdog
Timer is enabled. This ensures that the reset period will be in accordance with the
Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the
Watchdog Timer may not start counting from zero.
To avoid unintentional MCU Reset, the Watchdog Timer should be disabled or reset
before changing the Watchdog Timer Prescale Select.
Table 21. Watchdog Timer Prescale Select
WDP2
WDP1
WDP0
Number of WDT
Oscillator Cycles
Typical Time-out
at VCC = 3.0V
Typical Time-out
at VCC = 5.0V
0
16K cycles
47 ms
15 ms
0
1
32K cycles
94 ms
30 ms
0
1
0
64K cycles
0.19 s
60 ms
0
1
128K cycles
0.38 s
0.12 s
1
0
256K cycles
0.75 s
0,24 s
1
0
1
512K cycles
1.5 s
0.49 s
1
0
1,024K cycles
3.0 s
0.97 s
1
2,048K cycles
6.0 s
1.9 s
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