參數(shù)資料
型號: ATMEGA103-6AI
廠商: Atmel
文件頁數(shù): 81/141頁
文件大?。?/td> 0K
描述: IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 6MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
配用: ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
44
ATmega103(L)
0945I–AVR–02/07
Figure 32. Effects on Unsynchronized OCR Latching
During the time between the write and the latch operation, a read from OCR0 or OCR2
will read the contents of the temporary location. This means that the most recently writ-
ten value always will read out of OCR0/2.
When the OCR Register (not the temporary register) is updated to $00 or $FF, the PWM
output changes to low or high immediately according to the settings of COM21/COM20
or COM11/COM10. This is shown in Table 14.
Note:
n = 0 or 2
In PWM mode, the Timer Overflow Flag, TOV0 or TOV2, is set when the counter
advances from $00. Timer Overflow Interrupts 0 and 2 operate exactly as in normal
Timer/Counter mode, i.e., it is executed when TOV0 or TOV2 is set, provided that Timer
Overflow interrupt and Global Interrupts are enabled. This also applies to the Timer Out-
put Compare Flags and interrupts.
The frequency of the PWM will be Timer Clock Frequency divided by 510.
Asynchronous Status
Register – ASSR
Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and always read as zero.
Table 14. PWM Outputs OCRn = $00 or $FF
COMn1
COMn0
OCRn
Output PWMn
1
0
$00
L
10
$FF
H
1
$00
H
11
$FF
L
Counter Value
Compare Value
PWM Output
Synchronized OCR Latch
Counter Value
Compare Value
PWM Output
Unsynchronized OCR Latch
Glitch
Compare Value changes
Bit
7
6
543
2
1
0
$30 ($50)
––––
AS0
TCN0UB
OCR0UB
TCR0UB
ASSR
Read/Write
RRRR
R/W
R
Initial Value
0
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