參數(shù)資料
型號: ATMEGA103-6AI
廠商: Atmel
文件頁數(shù): 69/141頁
文件大小: 0K
描述: IC MCU 128K 6MHZ A/D IT 64TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 90
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 6MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
配用: ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
33
ATmega103(L)
0945I–AVR–02/07
Timer/Counter Interrupt Mask
Register – TIMSK
Bit 7 – OCIE2: Timer/Counter2 Output Compare Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at
vector $0012) is executed if a compare match in Timer/Counter2 occurs, i.e., when the
OCF2 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).
Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector
$0014) is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is
set in the Timer/Counter Interrupt Flag Register (TIFR).
Bit 5 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Input Capture Event interrupt is enabled. The corresponding interrupt
(at vector $0016) is executed if a capture-triggering event occurs on pin 29, PD4(IC1),
i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register.
Bit 4 – OCE1A: Timer/Counter1 Output Compare A Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare A Match interrupt is enabled. The corresponding interrupt (at
vector $0018) is executed if a Compare A Match in Timer/Counter1 occurs, i.e., when
the OCF1A bit is set in the Timer/Counter Interrupt Flag Register.
Bit 3 – OCIE1B: Timer/Counter1 Output Compare B Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare B Match interrupt is enabled. The corresponding interrupt (at
vector $001A) is executed if a Compare B Match in Timer/Counter1 occurs, i.e., when
the OCF1B bit is set in the Timer/Counter Interrupt Flag Register.
Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector
$001C) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is
set in the Timer/Counter Interrupt Flag Register.
Bit 1 – OCIE0: Timer/Counter0 Output Compare Interrupt Enable
When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt (at
vector $001E) is executed if a compare match in Timer/Counter0 occurs, i.e., when the
OCF0 bit is set in the Timer/Counter Interrupt Flag Register.
Bit
7
6
5
4
3
2
1
0
$37 ($57)
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
OCIE0
TOIE0
TIMSK
Read/Write
R/W
Initial Value
0
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