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參數(shù)資料
| 型號： | AM49BDS640AHE9I |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA89 |
| 封裝： | 10 X 8 MM, FBGA-89 |
| 文件頁數(shù)： | 77/84頁 |
| 文件大?。?/td> | 763K |
| 代理商： | AM49BDS640AHE9I |
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December 5, 2003
Am49BDS640AH
75
A D V A N C E I N F O R M A T I O N
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 1.8 V V
CC
, 1 million cycles. Additionally,
programming typicals assumes a checkerboard pattern.
2. Under worst case conditions of 90°C, V
CC
= 1.65 V 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 15, “Command Definitions,” on page 36 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1 million cycles.
BGA BALL CAPACITANCE
Notes:
1.
Sampled, not 100% tested.
2.
Test conditions T
A
= 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
32 Kword
0.4
5
s
Excludes 00h programming
prior to erasure (Note 4)
4 Kword
0.2
5
Chip Erase Time
103
s
Word Programming Time
9
210
μs
Excludes system level
overhead (Note 5)
Accelerated Word Programming Time
4
120
μs
Chip Programming Time (Note 3)
75.5
226.5
s
Excludes system level
overhead (Note 5)
Accelerated Chip Programming Time
33
99
s
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
4.2
5.0
pF
C
OUT
Output Capacitance
V
OUT
= 0
5.4
6.5
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
3.9
4.7
pF
Parameter
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
°
C
10
Years
125
°
C
20
Years
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