參數(shù)資料
型號(hào)： AM49BDS640AHE9I
廠商： SPANSION LLC
元件分類： 存儲(chǔ)器
英文描述： Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA89
封裝： 10 X 8 MM, FBGA-89
文件頁數(shù)： 56/84頁
文件大?。?/td> 763K
代理商： AM49BDS640AHE9I
54
Am49BDS640AH
December 5, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Note:
Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence
has been written with A18=0; device will output RDY with valid data.
1) RDY goes low during the two-cycle latency during a boundary crossing.
2) RDY stays high when a burst sequence crosses no boundaries.
Figure 22.
Standard Handshake Burst Suspend prior to Inital Access
Note:
Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence
has been written with A18=0; device will output RDY with valid data.
1) Burst suspend during the initial synchronous access
2) Burst suspend after one clock cycle following the initial synchronous access
Figure 23.
Standard Handshake Burst Suspend at or after Inital Access
Addresses
A(n)
AVD#
Data(2)
RDY(2)
RDY(1)
t
OES
t
OES
t
CKA
t
RACC
t
RACC
1
2
3
4
5
6
7
x+1
x+2
x+3
x+4
x+5
x+6
x
x+7
x+8
OE#
Data(1)
t
ACC
D(40)
D(3F)
D(n)
D(n+1)
D(n+2)
3F
3F
CLK
D(n)
D(n+1)
D(n+2)
D(n+3)
D(n+4)
D(n+5)
D(n+6)
Suspend
Resume
Addresses
A(n)
AVD#
OE#(1)
Data(1)
Data(2)
OE#(2)
RDY(1)
D(n)
D(n+1)
Suspend
7
Resume
x+1
t
ACC
t
RACC
t
OES
t
CKA
D(n)
t
OES
1
2
3
4
5
6
8
9
x
x+2
x+3
CLK
t
RACC
t
OES
t
RACC
t
CKA
D(n+1)
D(n+2)
D(n)
D(n+1)
t
RACC
t
RACC
t
RACC
t
CKZ
RDY(2)
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