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參數(shù)資料
| 型號： | AM49BDS640AHE9I |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA89 |
| 封裝： | 10 X 8 MM, FBGA-89 |
| 文件頁數(shù)： | 51/84頁 |
| 文件大?。?/td> | 763K |
| 代理商： | AM49BDS640AHE9I |
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December 5, 2003
Am49BDS640AH
49
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY
3. The device is in synchronous mode.
Figure 13.
CLK Synchronous Burst Mode Read (rising active CLK)
Notes:
1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active falling edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY
3. The device is in synchronous mode.
Figure 14.
CLK Synchronous Burst Mode Read (Falling Active Clock)
Da
Da + 1
Da + n
OE#
Data
Addresses
Aa
AVD#
RDY
CLK
CE#f
t
CES
t
ACS
t
AVC
t
AVD
t
ACH
t
OE
t
RACC
t
OEZ
t
CEZ
t
IACC
t
ACC
t
BDH
7 cycles for initial access shown.
Hi-Z
Hi-Z
Hi-Z
1
2
3
4
5
6
7
t
RDYS
t
BACC
t
CR
Da
Da + 1
Da + n
OE#
Data
Addresses
Aa
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVC
t
AVD
t
ACH
t
OE
t
OEZ
t
CEZ
t
IACC
t
ACC
t
BDH
4 cycles for initial access shown.
t
RACC
Hi-Z
Hi-Z
Hi-Z
1
2
3
4
5
t
RDYS
t
BACC
t
CR
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