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參數(shù)資料
| 型號： | AM49BDS640AHE9I |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA89 |
| 封裝： | 10 X 8 MM, FBGA-89 |
| 文件頁數(shù)： | 52/84頁 |
| 文件大小： | 763K |
| 代理商： | AM49BDS640AHE9I |
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50
Am49BDS640AH
December 5, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY
3. The device is in synchronous mode.
Figure 15.
Synchronous Burst Mode Read
Note:
Figure assumes 7 wait states for initial access and automatic detect synchronous read. D0–D7 in data waveform indicate
the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 7th address in
range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register command sequence
has been written with A18=1; device will output RDY with valid data.
Figure 16.
8-word Linear Burst with Wrap Around
Da
Da + 1
Da + n
OE#
Data
Addresses
Aa
AVD#
RDY
CLK
CE#
t
CAS
t
AAS
t
AVC
t
AVD
t
AAH
t
OE
t
RACC
t
OEZ
t
CEZ
t
IACC
t
BDH
7 cycles for initial access shown.
Hi-Z
Hi-Z
Hi-Z
1
2
3
4
5
6
7
t
RDYS
t
BACC
t
ACC
t
CR
D6
D7
OE#
Data
Addresses
A6
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVC
t
AVD
t
ACH
t
OE
t
IACC
t
ACC
t
BDH
D0
D1
D5
D6
7 cycles for initial access shown.
Hi-Z
t
RACC
1
2
3
4
5
6
7
t
RDYS
t
BACC
t
CR
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