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參數(shù)資料
| 型號： | AM49BDS640AHE8I |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA89 |
| 封裝： | 10 X 8 MM, FBGA-89 |
| 文件頁數(shù)： | 29/84頁 |
| 文件大小： | 763K |
| 代理商： | AM49BDS640AHE8I |
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December 5, 2003
Am49BDS640AH
27
A D V A N C E I N F O R M A T I O N
Table 10.
Programmable Wait State Settings
Notes:
1. Upon power-up or hardware reset, the default setting is
seven wait states.
2. RDY will default to being active with data when the Wait
State Setting is set to a total initial access cycle of 2.
It is recommended that the wait state command
sequence be written, even if the default wait state value
is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default set-
ting.
Reduced Wait-state Handshaking Option
If the device is equipped with the reduced wait-state
handshaking option, the host system should set
address bits A14–A12 to 010 for the system/device to
execute at maximum speed.
Table 11
describes the typical number of clock cycles
(wait states) for various conditions.
Table 11.
Wait States for Reduced wait-state
Handshaking
Notes:
1. If the latched address is 3Eh or 3Fh (or an address offset
from either address by a multiple of 64), add two access
cycles to the values listed.
2. In the 8-, 16-, and 32-word burst modes, the address
pointer does not cross 64-word boundaries (3Fh, or
addresses offset from 3Fh by a multiple of 64).
3. Typical initial access cycles may vary depending on
system margin requirements.
Standard Handshaking Option
For optimal burst mode performance on devices with
the standard handshaking option, the host system
must set the appropriate number of wait states in the
flash device depending on the clock frequency.
Table 12
describes the typical number of clock cycles
(wait states) for various conditions with A14-A12 set to
101.
Table 12.
Wait States for Standard Handshaking
* In the 8-, 16- and 32-word burst read modes, the address
pointer does not cross 64-word boundaries (addresses
which are multiples of 3Fh).
The autoselect function allows the host system to
determine whether the flash device is enabled for
handshaking. See the
“Autoselect Command
Sequence” section on page 29
for more information.
A14
A13
A12
Total Initial Access
Cycles
0
0
0
2
0
0
1
3
0
1
0
4
0
1
1
5
1
0
0
6
1
0
1
7 (default)
1
1
0
Reserved
1
1
1
Reserved
V
IO
= 1.8 V
System
Frequency
Range
Even Initial
Address
Odd Initial
Address
Device
Speed
Rating
6
–
22 MHz
2
2
D
(54 MHz)
22
–
28 MHz
2
3
28
–
43 MHz
3
4
43
–
54 MHz
4
5
6
–
28 MHz
2
2
E
(66 MHz)
28
–
35 MHz
2
3
35
–
53 MHz
3
4
53
–
66 MHz
4
5
Conditions at Address
Typical No. of Clock
Cycles after AVD# Low
Initial address
7
Initial address is 3E or 3Fh (or
offset from these addresses by
a multiple of 64) and is at
boundary crossing*
7
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