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參數(shù)資料
| 型號： | AM49BDS640AHE8I |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA89 |
| 封裝： | 10 X 8 MM, FBGA-89 |
| 文件頁數(shù)： | 14/84頁 |
| 文件大小： | 763K |
| 代理商： | AM49BDS640AHE8I |
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12
Am49BDS640AH
December 5, 2003
A D V A N C E I N F O R M A T I O N
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device.
Table 1
lists the device bus opera-
tions, the inputs and control levels they require, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1.
Device Bus Operations
Legend:
L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions.
Note:
Default active edge of CLK is the rising edge.
VersatileIO (V
IO
) Control
The VersatileIO
TM
(V
IO
) control allows the host system
to set the voltage levels that the device generates at its
data outputs and the voltages tolerated at its data
inputs to the same voltage level that is asserted on the
V
IO
pin.
Requirements for Asynchronous Read
Operation (Non-Burst)
To read data from the memory array, the system must
first assert a valid address on A22–A0, while driving
AVD# and CE# to V
IL
. WE# should remain at V
IH
. The
rising edge of AVD# latches the address. The data will
appear on DQ15–DQ0. Since the memory array is
divided into four banks, each bank remains enabled for
read access until the command register contents are
altered.
Address access time (t
ACC
) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from the stable
addresses and stable CE# to valid data at the outputs.
The output enable access time (t
OE
) is the delay from
the falling edge of OE# to valid data at the output.
The internal state machine is set for reading array data
in asynchronous mode upon device power-up, or after
a hardware reset. This ensures that no spurious alter-
ation of the memory content occurs during the power
transition.
Requirements for Synchronous (Burst)
Read Operation
The device is capable of continuous sequential burst
operation and linear burst operation of a preset length.
Operation
CE#
OE#
WE#
A22–0
DQ15–0
RESET#
CLK
(See
Note)
AVD#
Asynchronous Read - Addresses Latched
L
L
H
Addr In
I/O
H
X
Asynchronous Read - Addresses Steady State
L
L
H
Addr In
I/O
H
X
L
Asynchronous Write
L
H
L
Addr In
I/O
H
X
L
Synchronous Write
L
H
L
Addr In
I/O
H
Standby (CE#)
H
X
X
HIGH Z
HIGH Z
H
X
X
Hardware Reset
X
X
X
HIGH Z
HIGH Z
L
X
X
Burst Read Operations
Load Starting Burst Address
L
X
H
Addr In
X
H
Advance Burst to next address with appropriate
Data presented on the Data Bus
L
L
H
HIGH Z
Burst
Data Out
H
H
Terminate current Burst read cycle
H
X
H
HIGH Z
HIGH Z
H
X
Terminate current Burst read cycle via RESET#
X
X
H
HIGH Z
HIGH Z
L
X
X
Terminate current Burst read cycle and start
new Burst read cycle
L
X
H
HIGH Z
I/O
H
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