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參數(shù)資料
| 型號： | AM42BDS640AGTD9IT |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 8 X 11.60 MM, FBGA-93 |
| 文件頁數(shù)： | 59/72頁 |
| 文件大?。?/td> | 1060K |
| 代理商： | AM42BDS640AGTD9IT |
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58
Am42BDS640AG
November 1, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to
determine status. When the Embedded Algorithm
operation is complete, the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Burst Mode
Configuration Register). When A18 = 1 in the Burst Mode
Configuration Register, RDY is active one clock cycle before
data.
4. AVD# must toggle between data reads.
Figure 29.
Synchronous Data Polling Timings/Toggle Bit Timings
CE#f
CLK
AVD#
Addresses
OE#
Data
RDY
Status Data
Status Data
VA
VA
t
IACC
t
IACC
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