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參數資料
| 型號： | AM42BDS640AGTD9IT |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 8 X 11.60 MM, FBGA-93 |
| 文件頁數： | 13/72頁 |
| 文件大?。?/td> | 1060K |
| 代理商： | AM42BDS640AGTD9IT |
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12
Am42BDS640AG
November 1, 2002
P R E L I M I N A R Y
Table 1.
Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 9–11 V, V
HH
= 9.0 ± 0.5 V, X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
= Active edge of CLK,
= Pulse Low,
= Rising edge of Pulse Low
Notes:
1.
Other operations except for those indicated in this column are
inhibited.
Do not apply CE#f = V
IL
, CE1#s = V
IL
and CE2s = V
IH
at the same
time.
Either CE1#s = V
or CE2s = V
will disable the SRAM. If one of
these conditions is true, the other CE input is don’t care.
X = Don’t care or open LB#s or UB#s.
Default edge of CLK is the rising edge.
2.
3.
4.
5.
6.
The sector protect and sector unprotect functions may also be
implemented via programming equipment. See the
“Sector
Lock/Unlock Command Sequence”
section.
If ACC = V
HH
, all sectors will be protected.
If WP# = V
IL
, sectors 0,1 (bottom boot) or sectors 132, 133 (top
boot) are protected. If WP# = V
IH
, the protection applied to the
aforementioned sectors depends on whether they were last
protected or unprotected using the method described in
“Sector
Lock/Unlock Command Sequence”
. Note that WP# must not be left
floating or unconnected.
7.
8.
Operation
CE#f
CE1#s
CE2s
OE#
WE#
A
[21–0]
DQ
[15–8]
DQ
[7–0]
LB#s
UB#s
RESET#
CLK
AVD#
(Note 3)
(Note 4)
Asynchronous Read from Flash,
Addresses Latched
L
H
L
L
H
A
IN
I/O
X
X
H
X
Asynchronous Read from Flash,
Addresses Steady State
L
H
L
L
H
A
IN
I/O
X
X
H
X
L
Asynchronous Write to Flash
L
H
L
H
L
A
IN
I/O
X
X
H
X
L
Synchronous Write to Flash
L
H
L
H
L
A
IN
I/O
X
X
H
X
CE# Standby
H
H
L
X
X
Hi-Z
Hi-Z
X
X
H
X
X
Output Disable
L
H
L
H
H
Hi-Z
Hi-Z
Hi-Z
L
X
H
X
X
H
L
X
L
Hardware Reset
X
H
L
X
X
Hi-Z
Hi-Z
Hi-Z
X
X
L
X
X
Read from SRAM
H
L
H
L
H
A
IN
D
OUT
D
OUT
L
L
H
X
X
D
OUT
Hi-Z
H
L
Hi-Z
D
OUT
L
H
Wirte to SRAM
H
L
H
X
L
A
IN
D
IN
D
IN
L
L
H
X
X
D
IN
Hi-Z
H
L
HI-Z
D
IN
L
H
Flash Burst Read Operations
Load Starting Burst Address
L
H
L
X
H
Addr In
X
X
X
H
Advance Burst to next address with
appropriate Data presented on the
Data Bus
L
H
L
L
H
HIGH
Z
Burst
Data Out
X
X
H
H
Terminate current Burst read cycle
H
H
L
X
H
Hi-Z
Hi-Z
X
X
H
X
Terminate current Burst read cycle
via RESET#
X
H
L
X
H
Hi-Z
Hi-Z
X
X
L
X
X
Terminate current Burst read cycle
and start new Burst read cycle
L
H
L
X
H
Hi-Z
I/O
X
X
H
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