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參數(shù)資料
| 型號(hào)： | AM42BDS640AGTD9IT |
| 廠商： | SPANSION LLC |
| 元件分類(lèi)： | 存儲(chǔ)器 |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 8 X 11.60 MM, FBGA-93 |
| 文件頁(yè)數(shù)： | 52/72頁(yè) |
| 文件大?。?/td> | 1060K |
| 代理商： | AM42BDS640AGTD9IT |
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November 1, 2002
Am42BDS640AG
51
P R E L I M I N A R Y
AC CHARACTERISTICS
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid
Address for reading status bits.
2. “In progress” and “complete” refer to status of program
operation.
3. A21–A12 are don’t care during command sequence
unlock cycles.
4. CLK can be either V
IL
or V
IH
.
5. The Asynchronous programming operation is
independent of the Set Device Read Mode bit in the Burst
Mode Configuration Register.
6. AVD# must toggle during command sequence if CLK is at
V
IH
.
Figure 21.
Asynchronous Program Operation Timings
OE#
CE#f
Data
Addresses
AVD#
WE#
CLK
V
CC
555h
PD
t
AS
t
AVSW
t
AVHW
t
CSW1
t
AH
t
WC
t
WPH
PA
t
VCS
t
WP
t
DH
t
CH
In
Progress
t
WHWH1
VA
Complete
VA
Program Command Sequence (last two cycles)
Read Status Data
t
DS
V
IH
V
IL
t
AVDP
A0h
t
CS
(Note 4)
(Note 6)
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