參數(shù)資料
型號(hào)： AFE7222IRGC25
廠商： Texas Instruments
文件頁(yè)數(shù)： 98/106頁(yè)
文件大小： 0K
描述： IC AFE 12BIT 65/130MSPS 64VQFN
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
通道數(shù)： 4
功率（瓦特）： 610mW
電壓 - 電源，模擬： 2.85 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.7 V ~ 1.9 V
封裝/外殼： 64-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤(pán)（9x9）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 296-30067-6
TO GET INTO DIRECT ACCESS
MODE
SDATA
SCLK
SEN
AUX DAC A INPUT1
0
1
0
1
DA11 DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
AUX DAC B INPUT1
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB11
SDOUT
AUXDAC_A
AUXDAC_B
DELAY FOR FIRST UPDATE = 22 CLOCKS
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DA11
DB11
DB0
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB11
DA11
DELAY FOR SUBSEQUENT UPDATE = 12 CLOCKS
AUX DAC A INPUT2
AUX DAC B INPUT2
tPER
tSETTLE
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
AUXDAC_A_N is the internal complementary node and has an internal resistor, RINT programmable from
57 Ohm to 400 Ohm (using bits AUX_DAC_TERM_N<2:0>). For best linearity, choose a value of this
resistor to be as close to REXT as possible.
10.10 Enabling the Auxiliary DAC
The Auxiliary DACs are disabled by default.
Note that address of the 20 bit serial interface write bus is the 1st 12 bits out of which the 1st 4 bits
determine the access mode for the Auxiliary DAC.
Let us denote this address as ADDR<11:0>.
Following are Aux DAC modes:
If ADDR<11:8> = 0100, then we enter Direct Access mode for DAC. In this mode, DAC data is
dynamically written through SDATA (and SDOUT).
If ADDR<11:8> = 0101, then we enter the Register Access mode. In this mode, DAC is loaded with the
data from contents of pre-loaded registers.
In direct access mode
If ADDR<7:6> = 01: DAC_A will get written with the 12 serial bits from SDATA, DAC_B will get written
with the 12 serial bits from SDOUT (both at the rising edge of SCLK)
If ADDR<7:6> = 10: DAC_A will get 12 bits from SDATA, DAC_B will get next 12 bits from SDATA
(both at the rising edge of SCLK)
If ADDR<7:6> = 11: DAC_A will get 12 bits from SDATA at the rising edge of SCLK, DAC_B will get 12
bits from SDATA at the falling edge of SCLK.
In register access mode:
ADDR<7:6> = 01: Only DAC_A will be loaded with the register
ADDR<7:6> = 10: Only DAC_B will be loaded
ADDR<7:6> = 11: Both DAC_A and DAC_B are loaded.
For either direct access or register access modes, only the 1st 6 bits of the address need to be written for
the serial interface state machine. Remainig bits are considered as applicable to the DAC data.
Below diagram shows the Aux DAC timing for the direct access mode where DAC_A is written through
SDATA and DAC_B through SDOUT.
Start by already setting EN_AUXDACA and EN_AUXDACB bits high.
Figure 10-18. Aux DAC Timing Diagram: DAC_A is Written Through SDATA and DAC_B Through SDOUT
tPER = SCLK period > 25 ns
tSETTLE = Settling time of Aux DAC for full scale output (0-1.5V) = 40 ns
Copyright 2011–2012, Texas Instruments Incorporated
DIGITAL INTERFACE
91
Product Folder Link(s): AFE7222 AFE7225
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