參數(shù)資料
型號(hào): AFE7222IRGC25
廠商: Texas Instruments
文件頁數(shù): 104/106頁
文件大?。?/td> 0K
描述: IC AFE 12BIT 65/130MSPS 64VQFN
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
通道數(shù): 4
功率(瓦特): 610mW
電壓 - 電源,模擬: 2.85 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.7 V ~ 1.9 V
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 296-30067-6
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
Fast recovery powerdown mode through PDN pin : Set Address 207, Data 40, and control PDN pin to
assert/ de-assert fast recovery powerdown mode. RX and TX are both put to light sleep, for fast recovery.
Powerdown TX through PDN pin : Set Address 207, Data 02, and control PDN pin to assert/ de-assert
TX powerdown mode. In this mode, the TX path is shut down and the RX is fully active, but TX is waiting
for fast recovery.
Powerdown RX through PDN pin : Set Address 207, Data 04, and control PDN pin to assert/ de-assert
RX powerdown mode. In this mode, the RX path is shut down and the TX is fully active, but RX is waiting
for fast recovery.
In the above cases, the PDN pin was used to assert/ de-assert the powerdown state. Alternatively, a
register bit can be used to assert/ de-assert the powerdown state. This is bit D7 of register address 207.
The corresponding register configurations to assert/ de-assert the powerdown through the register bit are
as follows (in this case, keep the PDN pin low).
MODE
TO ASSERT POWERDOWN WRITE
TO DE-ASSERT POWERDOWN WRITE
Global powerdown through register
Address 207, Data A0
Address 207, Data 20
Fast recovery powerdown through register
Address 207, Data C0
Address 207, Data 40
TX powerdown through register
Address 207, Data 82
Address 207, Data 02
RX powerdown through register
Address 207, Data 84
Address 207, Data 04
Copyright 2011–2012, Texas Instruments Incorporated
QUICK GUIDE
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Product Folder Link(s): AFE7222 AFE7225
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