th tsu t
參數(shù)資料
型號(hào)： AFE7222IRGC25
廠商： Texas Instruments
文件頁數(shù)： 90/106頁
文件大?。?/td> 0K
描述： IC AFE 12BIT 65/130MSPS 64VQFN
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
通道數(shù)： 4
功率（瓦特）： 610mW
電壓 - 電源，模擬： 2.85 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.7 V ~ 1.9 V
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 296-30067-6
DAC_DCLK
DACDATA
Ch A
Ch B
th
tsu
th
tsu
t
CLK/6
DAC_DCLK
DAC_DATA
Ch A
Ch B
th
tsu
th
tsu
t
/3
CLK
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
A.
tCLK = Time period of DAC input data clock (same as time period of DAC output clock when interpolation is set to 1).
B.
th is minimum hold time required at the AFE722x input.
C.
tsu is minimum setup time required at the AFE722x input.
Figure 10-5. TX 1-Wire Mode Timing Diagram
2-Wire mode, DDR clock: 2 LVDS pairs for the data to each DAC. It will operate in a DDR fashion
serialized to a frequency of 3x the pattern word rate. A frame clock (DAC_FCLKINP/N) at half the word
rate and a bit clock (DAC_DCLKINP/N) at 3x. Example: 50MSPS 12-bit pattern will serialize to
150MHz on each LVDS pair, frame clock of 25MHz and bit clock of 150MHz. Effective serial data rate
is 300Mbps on each LVDS pair due to bit transitions on rising and falling edge of bit clock.
Recommended maximum word rate is ~125MSPS in this mode.
A.
tCLK = Time period of DAC input data clock (same as time period of DAC output clock when interpolation is set to 1).
B.
th is minimum hold time required at the AFE722x input.
C.
tsu is minimum setup time required at the AFE722x input.
Figure 10-6. TX 2-Wire Mode, DDR Clock Timing Diagram
2-Wire mode, SDR clock: 2 LVDS pairs for the data to each DAC. It will operate in a SDR fashion
serialized to a frequency of 6x the pattern word rate. A frame clock (DAC_FCLKINP/N) at the word rate
and a bit clock (DAC_DCLKINP/N) at 6x. Example: 50MSPS 12-bit pattern will serialize to 300MHz on
each LVDS pair, frame clock of 50MHz and bit clock of 300MHz. Effective serial data rate is 300Mbps
on each LVDS pair due to bit transitions on rising edge of bit clock. Recommended maximum word
rate is ~65MSPS in this mode.
84
DIGITAL INTERFACE
Copyright 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): AFE7222 AFE7225
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AFE7222IRGCR 功能描述:射頻前端 Dual 12B,65MSPS ADC RoHS:否 制造商:Skyworks Solutions, Inc. 類型: 工作頻率:2.4 GHz, 5 GHz 最大數(shù)據(jù)速率:54 Mbps 噪聲系數(shù): 工作電源電壓:3.3 V 電源電流:180 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-32
AFE7222IRGCT 功能描述:射頻前端 Dual 12B,65MSPS ADC RoHS:否 制造商:Skyworks Solutions, Inc. 類型: 工作頻率:2.4 GHz, 5 GHz 最大數(shù)據(jù)速率:54 Mbps 噪聲系數(shù): 工作電源電壓:3.3 V 電源電流:180 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-32
AFE7225 制造商:TI 制造商全稱:Texas Instruments 功能描述:Analog Front End Wideband Mixed-Signal Transceiver
AFE7225EVM 功能描述:射頻開發(fā)工具 AFE7225 Eval Mod RoHS:否 制造商:Taiyo Yuden 產(chǎn)品:Wireless Modules 類型:Wireless Audio 工具用于評(píng)估:WYSAAVDX7 頻率: 工作電源電壓:3.4 V to 5.5 V
AFE7225IRGC25 功能描述:射頻前端 Dual 12B,125MSPS ADC RoHS:否 制造商:Skyworks Solutions, Inc. 類型: 工作頻率:2.4 GHz, 5 GHz 最大數(shù)據(jù)速率:54 Mbps 噪聲系數(shù): 工作電源電壓:3.3 V 電源電流:180 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-32
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