參數(shù)資料
型號(hào)： ADV7343BSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 59/108頁
文件大小： 0K
描述： IC ENCODER VIDEO W/DAC 64-LQFP
產(chǎn)品變化通告： ADV734x, ADV739x Feature Improvement
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編碼器
應(yīng)用： DVD，Blu-Ray
電壓 - 電源，模擬： 3.3V
電壓 - 電源，數(shù)字： 1.8V
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
ADV7342/ADV7343
Data Sheet
Rev. | Page 54 of 108
SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for non-
standard input video, that is, in fast forward or rewind mode.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields is reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields is
reached. Conventionally, this means that the output video has
corrupted field signals because one signal is generated by the
incoming video and another is generated when the internal
line/field counters reach the end of a field.
When the VCR FF/RW sync control is enabled (Subaddress 0x82,
Bit 5), the line/field counters are updated according to the
incoming VSYNC signal and when the analog output matches
the incoming VSYNC signal.
This control is available in all slave-timing modes except Slave
Mode 0.
VERTICAL BLANKING INTERVAL
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
The ADV7342/ADV7343 are able to accept input data that
contains VBI data (such as CGMS, WSS, and VITS) in SD, ED,
and HD modes.
If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD;
Subaddress 0x83, Bit 4 for SD), VBI data is not present at the
output and the entire VBI is blanked. These control bits are
valid in all master and slave timing modes.
For the SMPTE 293M (525p) standard, VBI data can be
inserted on Line 13 to Line 42 of each frame or on Line 6 to
Line 43 for the ITU-R BT.1358 (625p) standard.
VBI data can be present on Line 10 to Line 20 for NTSC and on
Line 7 to Line 22 for PAL.
In SD Timing Mode 0 (slave option), if VBI is enabled, the
blanking bit in the EAV/SAV code is overwritten. It is possible
to use VBI in this timing mode as well.
If CGMS is enabled and VBI is disabled, the CGMS data is,
nevertheless, available at the output.
SD SUBCARRIER FREQUENCY CONTROL
Subaddress 0x8C to Subaddress 0x8F
The ADV7342/ADV7343 are able to generate the color subcarrier
used in CVBS and S-Video (Y-C) outputs from the input pixel
clock. Four 8-bit registers are used to set up the subcarrier
frequency. The value of these registers is calculated using
32
2
MHz
27
×
=
line
video
one
in
cycles
clk
of
Number
line
video
one
in
periods
subcarrier
of
Number
Register
Frequency
Subcarrier
where the sum is rounded to the nearest integer.
For example, in NTSC mode
569408543
2
1716
5
.
227
32
=
×
=
Value
Register
Subcarrier
where:
Subcarrier Register Value = 569408543d = 0×21F07C1F
SD FSC Register 0: 0x1F
SD FSC Register 1: 0x7C
SD FSC Register 2: 0xF0
SD FSC Register 3: 0x21
Programming the FSC
The subcarrier frequency register value is divided into four FSC
registers as shown in the previous example. The four subcarrier
frequency registers must be updated sequentially, starting with
Subcarrier Frequency Register 0 and ending with Subcarrier
Frequency Register 3. The subcarrier frequency updates only
after the last subcarrier frequency register byte is received by
the ADV7342/ADV7343. The SD input standard autodetection
feature must be disabled.
Typical FSC Values
Table 42 outlines the values that should be written to the
subcarrier frequency registers for NTSC and PAL B/D/G/H/I.
Table 42. Typical FSC Values
Subaddress
Description
NTSC
PAL B/D/G/H/I
0x8C
FSC0
0x1F
0xCB
0x8D
FSC1
0x7C
0x8A
0x8E
FSC2
0xF0
0x09
0x8F
FSC3
0x21
0x2A
SD NONINTERLACED MODE
Subaddress 0x88, Bit 1
The ADV7342/ADV7343 support an SD noninterlaced mode.
Using this mode, progressive inputs at twice the frame rate of
NTSC and PAL (240p/59.94 Hz and 288p/50 Hz, respectively)
can be input into the ADV7342/ADV7343. The SD noninterlaced
mode can be enabled using Subaddress 0x88, Bit 1.
A 27 MHz clock signal must be provided on the CLKIN_A pin.
Embedded EAV/SAV timing codes or external horizontal and
vertical synchronization signals provided on the S_HSYNC and
S_VSYNC pins can be used to synchronize the input pixel data.
All input configurations, output configurations, and features
available in NTSC and PAL modes are available in SD non-
interlaced mode.
For 240p/59.94 Hz input, the ADV7342/ ADV7343 should be
configured for NTSC operation, and Subaddress 0x88, Bit 1
should be set to 1.
For 288p/50 Hz input, the ADV7342/ADV7343 should be
configured for PAL operation, and Subaddress 0x88, Bit 1
should be set to 1.
D
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ADV7343WBSTZ 功能描述:IC ENCODER VID 12BIT DAC 64LQFP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:視頻編碼器 應(yīng)用:DVD，Blu-Ray 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商器件封裝:64-LQFP（10x10） 標(biāo)準(zhǔn)包裝:1
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