參數(shù)資料
型號： ADV7343BSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 107/108頁
文件大?。?/td> 0K
描述： IC ENCODER VIDEO W/DAC 64-LQFP
產(chǎn)品變化通告： ADV734x, ADV739x Feature Improvement
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編碼器
應(yīng)用： DVD，Blu-Ray
電壓 - 電源，模擬： 3.3V
電壓 - 電源，數(shù)字： 1.8V
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
ADV7342/ADV7343
Data Sheet
Rev. | Page 98 of 108
ENHANCED DEFINITION
Table 85. ED Configuration Scripts
Input Format
Input Data Width1
Synchronization Format
Input Color Space
Output Color Space
Table Number
525p at 59.94 Hz
8-bit DDR
EAV/SAV
YCrCb
YPrPb
525p at 59.94 Hz
8-bit DDR
HSYNC/VSYNC
YCrCb
YPrPb
525p at 59.94 Hz
8-bit DDR
EAV/SAV
YCrCb
RGB
525p at 59.94 Hz
16-bit SDR
EAV/SAV
YCrCb
YPrPb
525p at 59.94 Hz
16-bit SDR
HSYNC/VSYNC
YCrCb
YPrPb
525p at 59.94 Hz
16-bit SDR
EAV/SAV
YCrCb
RGB
525p at 59.94 Hz
16-bit SDR
HSYNC/VSYNC
YCrCb
RGB
525p at 59.94 Hz
24-bit SDR
EAV/SAV
YCrCb
YPrPb
525p at 59.94 Hz
24-bit SDR
HSYNC/VSYNC
YCrCb
YPrPb
525p at 59.94 Hz
24-bit SDR
EAV/SAV
YCrCb
RGB
525p at 59.94 Hz
24-bit SDR
HSYNC/VSYNC
YCrCb
RGB
525p at 59.94 Hz
24-bit SDR
HSYNC/VSYNC
RGB
625p at 50 Hz
8-bit DDR
EAV/SAV
YCrCb
YPrPb
625p at 50 Hz
8-bit DDR
HSYNC/VSYNC
YCrCb
YPrPb
625p at 50 Hz
8-bit DDR
EAV/SAV
YCrCb
RGB
625p at 50 Hz
8-bit DDR
HSYNC/VSYNC
YCrCb
RGB
625p at 50 Hz
16-bit SDR
EAV/SAV
YCrCb
YPrPb
625p at 50 Hz
16-bit SDR
HSYNC/VSYNC
YCrCb
YPrPb
625p at 50 Hz
16-bit SDR
EAV/SAV
YCrCb
RGB
625p at 50 Hz
16-bit SDR
HSYNC/VSYNC
YCrCb
RGB
625p at 50 Hz
24-bit SDR
EAV/SAV
YCrCb
YPrPb
625p at 50 Hz
24-bit SDR
HSYNC/VSYNC
YCrCb
YPrPb
625p at 50 Hz
24-bit SDR
EAV/SAV
YCrCb
RGB
625p at 50 Hz
24-bit SDR
HSYNC/VSYNC
YCrCb
RGB
625p at 50 Hz
24-bit SDR
HSYNC/VSYNC
RGB
1
SDR = single data rate; DDR = dual data rate.
Table 86. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x04
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 87. 8-Bit 525p YCrCb In, YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x00
525p at 59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
0x31
0x01
Pixel data valid.
Table 88. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x04
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 89. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x10
ED-SDR input mode.
0x30
0x04
525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
D
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