參數(shù)資料
型號(hào)： ADV7343BSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 106/108頁
文件大?。?/td> 0K
描述： IC ENCODER VIDEO W/DAC 64-LQFP
產(chǎn)品變化通告： ADV734x, ADV739x Feature Improvement
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編碼器
應(yīng)用： DVD，Blu-Ray
電壓 - 電源，模擬： 3.3V
電壓 - 電源，數(shù)字： 1.8V
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
Data Sheet
ADV7342/ADV7343
Rev. | Page 97 of 108
Table 79. 16-Bit 625i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0xFC
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x80
0x11
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82
0xC1
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
0x88
0x08
16-bit input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 80. 16-Bit 625i YCrCb In, RGB and CVBS/Y-C Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0xFC
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x80
0x11
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82
0xC1
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
0x88
0x08
16-bit input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 81. 24-Bit 625i RGB In, YPrPb and CVBS/Y-C Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0xFC
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x80
0x11
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82
0xC1
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
0x87
0x80
RGB input enabled.
0x88
0x10
24-Bit RGB input enabled
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 82. 24-Bit 625i RGB In, RGB and CVBS/Y-C Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0xFC
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x80
0x11
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82
0xC1
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
0x87
0x80
RGB input enabled.
0x88
0x10
24-bit RGB input enabled
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 83. 8-Bit PAL Square Pixel YCrCb In (EAV/SAV),
CVBS/Y-C Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x80
0x11
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82
0xD3
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Square
pixel mode enabled.
0x8C
0x0C
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL square pixel mode (29.5 MHz
input clock).
0x8D
0x8C
0x8E
0x79
0x8F
0x26
Table 84. 16-Bit PAL Square Pixel RGB In, CVBS/Y-C Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x80
0x11
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82
0xD3
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Square
pixel mode enabled.
0x87
0x80
RGB input enabled.
0x88
0x10
16-bit RGB input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
0x8C
0x0C
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL square pixel mode (29.5 MHz
input clock).
0x8D
0x8C
0x8E
0x79
0x8F
0x26
D
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