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參數(shù)資料
| 型號： | ADV7343BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 58/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ENCODER VIDEO W/DAC 64-LQFP |
| 產(chǎn)品變化通告： | ADV734x, ADV739x Feature Improvement |
| 標準包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應用： | DVD，Blu-Ray |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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Data Sheet
ADV7342/ADV7343
Rev.
| Page 53 of 108
HD INTERLACE EXTERNAL P_HSYNC AND
P_VSYNC CONSIDERATIONS
If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 01
or higher, the user should set Subaddress 0x02, Bit 1 to high to
ensure exactly correct timing in HD interlace modes when
using the P_HSYNCand P_VSYNC synchronization signals. If
this bit is set to low, the first active pixel on each line is masked
and the Pr and Pb outputs are swapped when using the YCrCb
4:2:2 input format. Setting Subaddress 0x02, Bit 1 to low causes
the encoder to behave in the same way as the first version of
silicon (that is, this setting is backward compatible).
If the encoder revision code (Subaddress 0xBB, Bits[7:6] = 00,
the setting of Subaddress 0x02, Bit1 has no effect. In this version
of the encoder, the first active pixel is masked and Pr and Pb
outputs are swapped when using the YCrCb 4:2:2 input format.
To avoid these limitations, use the newer version of silicon or a
different type of synchronization.
These considerations apply only to the HD interlace modes
with external P_HSYNCand P_VSYNC synchronization
(EAV/SAV mode is not affected and always has exactly correct
timing). There is no negative effect in setting Subaddress 0x02,
Bit 0 to high, and this bit can remain high for all the other video
standards.
ED/HD TIMING RESET
Subaddress 0x34, Bit 0
An ED/HD timing reset is achieved by toggling the ED/HD
timing reset control bit (Subaddress 0x34, Bit 0) from 0 to 1.
In this state, the horizontal and vertical counters remain reset.
When this bit is set back to 0, the internal counters resume
counting. This timing reset applies to the ED/HD timing
counters only.
SD SUBCARRIER FREQUENCY LOCK
Subcarrier Frequency Lock (SFL) Mode
In this mode (Subaddress 0x84, Bits[2:1] = 11), the ADV7342/
ADV7343 can be used to lock to an external video source. The
SFL mode allows the ADV7342/ADV7343 to automatically alter
the subcarrier frequency to compensate for line length variations.
When the part is connected to a device such as an ADV7403 video
decoder (see Figure 59) that outputs a digital data stream in the
SFL format, the part automatically changes to the compensated
subcarrier frequency on a line-by-line basis. This digital data
stream is 67 bits wide, and the subcarrier is contained in Bit 0 to
Bit 21. Each bit is two clock cycles long.
LLC1
SFL
P[19:12]
ADV7403
VIDEO
DECODER
CLKIN_A
SFL
Y[7:0]/S[7:0]5
RTC
LOW
128
TIME SLOT 01
13
0
14
21
19
FSC PLL INCREMENT2
VALID
SAMPLE
INVALID
SAMPLE
6768
0
RESET BIT4
RESERVED
ADV7342/ADV7343
8/LINE
LOCKED
CLOCK
5 BITS
RESERVED
1FOR EXAMPLE, VCR OR CABLE.
2FSC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7342/ADV7343 FSC DDS REGISTER IS
FSC PLL INCREMENTS BITS[21:0] PLUS BITS[0:9] OF SUBCARRIER FREQUENCY REGISTERS.
3SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
4RESET ADV7342/ADV7343 DDS.
5SELECTED BY SUBADDRESS 0x01, BIT 7.
COMPOSITE
VIDEO1
H/L TRANSITION
COUNT START
14 BITS
SUBCARRIER
PHASE
SEQUENCE
BIT3
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
4 BITS
RESERVED
0
6399-
063
Figure 59. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)
D
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