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參數(shù)資料
| 型號： | ADV7343BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 53/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ENCODER VIDEO W/DAC 64-LQFP |
| 產(chǎn)品變化通告： | ADV734x, ADV739x Feature Improvement |
| 標準包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | DVD，Blu-Ray |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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Data Sheet
ADV7342/ADV7343
Rev. | Page 49 of 108
MPEG2
DECODER
CLKIN_A
S[7:0] OR Y[7:0]*
27MHz
YCrCb
ADV7342/
ADV7343
*SELECTED BY SUBADDRESS 0x01, BIT 7.
S_VSYNC,
S_HSYNC
2
8
06399-
051
Figure 51. SD Only Example Application
ENHANCED DEFINITION/HIGH DEFINITION ONLY
Subaddress 0x01, Bits[6:4] = 001 or 010
Enhanced definition (ED) or high definition (HD) YCrCb data
can be input in either 4:2:2 or 4:4:4 format. If desired, dual data
rate (DDR) pixel data inputs can be employed (4:2:2 format only).
Enhanced definition (ED) or high definition (HD) RGB data
can be input in 4:4:4 format (single data rate only).
The clock signal must be provided on the CLKIN_A pin. Input
synchronization signals are provided on the P_HSYNC, P_VSYNC,
and P_BLANK pins.
16-Bit 4:2:2 YCrCb Mode (SDR)
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin Y7 to Pin Y0, with Pin Y0 being the LSB. The CrCb pixel
data is input on Pin C7 to Pin C0, with Pin C0 being the LSB.
8-Bit 4:2:2 YCrCb Mode (DDR)
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1
In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input
on Pin Y7 to Pin Y0 on either the rising or falling edge of
CLKIN_A. Pin Y0 is the LSB.
The CrCb pixel data is also input on Pin Y7 to Pin Y0 on the
opposite edge of CLKIN_A. Pin Y0 is the LSB. Whether the Y
data is clocked in on the rising or falling edge of CLKIN_A is
determined by Subaddress 0x01, Bits[2:1] (see Figure 52 and
3FF
00
XY
Y0
Y1
Cr0
CLKIN_A
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
Y[7:0]
Cb0
06399-
052
Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
3FF
00
XY
Cb0
Cr0
Y1
CLKIN_A
Y[7:0]
Y0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
06399-
053
Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
24-Bit 4:4:4 YCrCb Mode
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 0
In 24-bit 4:4:4 YCrCb input mode, the Y pixel data is input on
Pin Y7 to Pin Y0, with Pin Y0 being the LSB.
The Cr pixel data is input on Pin S7 to Pin S0, with Pin S0 being
the LSB. The Cb pixel data is input on Pin C7 to Pin C0, with
Pin C0 being the LSB.
24-Bit 4:4:4 RGB Mode
Subaddress 0x35, Bit 1 = 1
In 24-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin S7 to Pin S0, the green pixel data is input on Pin Y7 to Pin Y0,
and the blue pixel data is input on Pin C7 to Pin C0. The S0, Y0,
and C0 pins are the respective bus LSBs.
MPEG2
DECODER
CLKIN_A
C[7:0]
S[7:0]
Y[7:0]
INTERLACED TO
PROGRESSIVE
YCrCb
P_VSYNC,
P_HSYNC,
P_BLANK
8
Cb
8
Cr
8
Y
3
06399-
054
ADV7342/
ADV7343
Figure 54. ED/HD Only Example Application
SIMULTANEOUS STANDARD DEFINITION AND
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 011 or 100
The ADV7342/ADV7343 are able to simultaneously process SD
4:2:2 YCrCb data and ED/HD 4:2:2 YCrCb data. The 27 MHz
SD clock signal must be provided on the CLKIN_A pin. The
ED/HD clock signal must be provided on the CLKIN_B pin.
SD input synchronization signals are provided on the S_HSYNC
and S_VSYNC pins. ED/HD input synchronization signals are
provided on the P_HSYNC, P_VSYNC and P_BLANK pins.
SD 8-Bit 4:2:2 YCrCb and ED/HD-SDR 16-Bit 4:2:2 YCrCb
The SD 8-bit 4:2:2 YCrCb pixel data is input on Pin S7 to Pin S0,
with Pin S0 being the LSB.
The ED/HD 16-bit 4:2:2 Y pixel data is input on Pin Y7 to Pin Y0,
with Pin Y0 being the LSB.
The ED/HD 16-bit 4:2:2 CrCb pixel data is input on Pin C7 to
Pin C0, with Pin C0 being the LSB.
SD 8-Bit 4:2:2 YCrCb and ED/HD-DDR 8-Bit 4:2:2 YCrCb
The SD 8-bit 4:2:2 YCrCb pixel data is input on Pin S7 to Pin S0,
with Pin S0 being the LSB. The ED/HD-DDR 8-bit 4:2:2 Y pixel
data is input on Pin Y7 to Pin Y0 on the rising or falling edge of
CLKIN_B. Pin Y0 is the LSB.
The ED/HD-DDR 8-bit 4:2:2 CrCb pixel data is also input on
Pin Y7 to Pin Y0 on the opposite edge of CLKIN_B. Pin Y0 is
the LSB.
D
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| ADV7343WBSTZ | 功能描述:IC ENCODER VID 12BIT DAC 64LQFP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:視頻編碼器 應(yīng)用:DVD，Blu-Ray 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商器件封裝:64-LQFP（10x10） 標準包裝:1 |
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| ADV7344BSTZ | 制造商:Analog Devices 功能描述: |
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