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| 型號： | ADUC824BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 60/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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REV. B
ADuC824
–63–
LATCH
ADuC824
RD
P2
ALE
P0
WR
LATCH
SRAM
OE
A8–A15
A0–A7
D0–D7
(DATA)
WE
A16–A23
Figure 46. External Data Memory Interface (16 MBytes
Address Space)
In either implementation, Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the data pointer (DPL) as
an address, which is latched by a pulse of ALE prior to data being
placed on the bus by the ADuC824 (write operation) or the
SRAM (read operation). Port 2 (P2) provides the data pointer
page byte (DPP) to be latched by ALE, followed by the data
pointer high byte (DPH). If no latch is connected to P2, DPP is
ignored by the SRAM, and the 8051 standard of 64 Kbyte external
data memory access is maintained.
Detailed timing diagrams of external program and data memory
read and write access can be found in the timing specification
sections of this data sheet.
Power-On Reset Operation
External POR (power-on reset) circuitry must be implemented to
drive the RESET pin of the ADuC824. The circuit must hold
the RESET pin asserted (high) whenever the power supply
(DVDD) is below 2.5 V. Furthermore, VDD must remain above
2.5 V for at least 10 ms before the RESET signal is deasserted
(low) by which time the power supply must have reached at
least a 2.7 V level. The external POR circuit must be opera-
tional down to 1.2 V or less. The timing diagram of Figure 47
illustrates this functionality under three separate events: power-
up, brownout, and power-down. Notice that when RESET is
asserted (high) it tracks the voltage on DVDD.
10ms
MIN
1.2V MAX
10ms
MIN
2.5V MIN
1.2V MAX
DVDD
RESET
Figure 47. External POR Timing
The best way to implement an external POR function to meet
the above requirements involves the use of a dedicated POR chip,
such as the ADM809/ADM810 SOT-23 packaged PORs from
Analog Devices. Recommended connection diagrams for both
active-high ADM810 and active-low ADM809 PORs are shown
in Figure 48 and Figure 49 respectively.
DVDD
RESET
48
34
20
15
ADuC824
POR
(ACTIVE HIGH)
POWER SUPPLY
Figure 48. External Active High POR Circuit
Some active-low POR chips, such as the ADM809 can be used with
a manual push-button as an additional reset source as illustrated
by the dashed line connection in Figure 49.
DVDD
RESET
48
34
20
ADuC824
15
OPTIONAL
MANUAL RESET
PUSH-BUTTON
POR
(ACTIVE LOW)
POWER SUPPLY
1k
Figure 49. External Active Low POR Circuit
Power Supplies
The ADuC824’s operational power supply voltage range is 2.7 V
to 5.25 V. Although the guaranteed data sheet specifications are
given only for power supplies within 2.7 V to 3.6 V or +5% of
the nominal 5 V level, the chip will function equally well at any
power supply level between 2.7 V and 5.25 V.
Separate analog and digital power supply pins (AVDD and DVDD
respectively) allow AVDD to be kept relatively free of noisy digital
signals often present on the system DVDD line. In this mode the
part can also operate with split supplies; that is, using different
voltage supply levels for each supply. For example, this means that
the system can be designed to operate with a DVDD voltage level
of 3 V while the AVDD level can be at 5 V or vice versa if required.
A typical split supply configuration is show in Figure 50.
DVDD
48
34
20
ADuC824
5
6
AGND
AVDD
–
+
0.1 F
10 F
ANALOG SUPPLY
10 F
DGND
35
21
47
0.1 F
–
+
DIGITAL SUPPLY
Figure 50. External Dual Supply Connections
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