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| 型號： | ADUC824BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 58/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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REV. B
ADuC824
–61–
IEIP2
Secondary Interrupt Enable and Priority Register
SFR Address
A9H
Power-On Default Value
A0H
Bit Addressable
No
—
I
T
PM
S
P
PI
S
P
—
I
T
EM
S
P
EI
S
E
Table XXXII. IEIP2 SFR Bit Designations
Bit
Name
Description
7
—
Reserved for Future Use
6
PTI
Written by User to Select TIC Interrupt Priority (‘1’ = High; ‘0’ = Low).
5
PPSM
Written by User to Select Power Supply Monitor Interrupt Priority (‘1’ = High; ‘0’ = Low).
4
PSI
Written by User to Select SPI/I
2C Serial Port Interrupt Priority (‘1’ = High; ‘0’ = Low).
3
—
Reserved, This Bit Must Be ‘0.’
2
ETI
Written by User to Enable ‘1’ or Disable ‘0’ TIC Interrupt.
1
EPSM
Written by User to Enable ‘1’ or Disable ‘0’ Power Supply Monitor Interrupt.
0
ESI
Written by User to Enable ‘1’ or Disable ‘0’ SPI/I
2C Serial Port Interrupt.
Interrupt Priority
The Interrupt Enable registers are written by the user to enable
individual interrupt sources, while the Interrupt Priority registers
allow the user to select one of two priority levels for each interrupt. An
interrupt of a high priority may interrupt the service routine of a low
priority interrupt, and if two interrupts of different priority occur
at the same time, the higher level interrupt will be serviced first. An
interrupt cannot be interrupted by another interrupt of the same
priority level. If two interrupts of the same priority level occur simulta-
neously, a polling sequence is observed as shown in Table XXXIII.
Table XXXIII. Priority within an Interrupt Level
Source
Priority
Description
PSMI
1 (Highest)
Power Supply Monitor Interrupt
WDS
2
Watchdog Interrupt
IE0
3
External Interrupt 0
RDY0/RDY1
4
ADC Interrupt
TF0
5
Timer/Counter 0 Interrupt
IE1
6
External Interrupt 1
TF1
7
Timer/Counter 1 Interrupt
I2CI + ISPI
8
I
2C/SPI Interrupt
RI + TI
9
Serial Interrupt
TF2 + EXF2
10
Timer/Counter 2 Interrupt
TII
11 (Lowest)
Time Interval Counter Interrupt
Interrupt Vectors
When an interrupt occurs the program counter is pushed onto the
stack and the corresponding interrupt vector address is loaded into
the program counter. The interrupt vector addresses are shown
in Table XXXIV.
Table XXXIV. Interrupt Vector Addresses
Source
Vector Address
IE0
0003 Hex
TF0
000B Hex
IE1
0013 Hex
TF1
001B Hex
RI + TI
0023 Hex
TF2 + EXF2
002B Hex
RDY0/RDY1 (ADC)
0033 Hex
II
2C + ISPI
003B Hex
PSMI
0043 Hex
TII
0053 Hex
WDS (WDIR = 1)
*
005B Hex
*The watchdog can be configured to generate an interrupt instead of a reset when it
times out. This is used for logging errors or to examine the internal status of the
microcontroller core to understand, from a software debug point of view, why a
watchdog timeout occurred. The watchdog interrupt is slightly different from the
normal interrupts in that its priority level is always set to 1 and it is not possible
to disable the interrupt via the global disable bit ( EA) in the IE SFR. This is
done to ensure that the interrupt will always be responded to if a watch dog
timeout occurs. The watchdog will only produce an interrupt if the watchdog
timeout is greater than zero.
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