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參數資料
| 型號： | ADUC824BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 29/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 52MQFP |
| 標準包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數： | 34 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數據轉換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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REV. B
ADuC824
–35–
Excitation Currents
The ADuC824 also contains two identical 200
A constant
current sources. Both source current from AVDD to Pin #3
(IEXC1) or Pin #4 (IEXC2). These current sources are con-
trolled via bits in the ICON SFR shown in Table VIII. They
can be configured to source 200
A individually to both pins or
a combination of both currents, i.e., 400
A to either of the
selected pins. These current sources can be used to excite exter-
nal resistive bridge or RTD sensors.
Reference Input
The ADuC824’s reference inputs, REFIN(+) and REFIN(–),
provide a differential reference input capability. The common-
mode range for these differential inputs is from AGND to AVDD.
The nominal reference voltage, VREF (REFIN(+) – REFIN(–)),
for specified operation is 2.5 V with the primary and auxil-
iary reference enable bits set in the respective ADC0CON
and/or ADC1CON SFRs.
The part is also functional (although not specified for perfor-
mance) when the XREF0 or XREF1 bits are ‘0,’ which enables
the on-chip internal bandgap reference. In this mode, the ADCs
will see the internal reference of 1.25 V, therefore halving all
input ranges. As a result of using the internal reference volt-
age, a noticeable degradation in peak-to-peak resolution will
result. Therefore, for best performance, operation with an exter-
nal reference is strongly recommended.
In applications where the excitation (voltage or current) for the
transducer on the analog input also drives the reference voltage
for the part, the effect of the low-frequency noise in the excita-
tion source will be removed as the application is ratiometric. If the
ADuC824 is not used in a ratiometric application, a low noise
reference should be used. Recommended reference voltage sources
for the ADuC824 include the AD780, REF43, and REF192.
It should also be noted that the reference inputs provide a high
impedance, dynamic load. Because the input impedance of each
reference input is dynamic, resistor/capacitor combinations on
these inputs can cause dc gain errors depending on the output
impedance of the source that is driving the reference inputs.
Reference voltage sources, like those recommended above (e.g.,
AD780) will typically have low output impedances and therefore
decoupling capacitors on the REFIN(+) input would be recom-
mended. Deriving the reference input voltage across an external
resistor, as shown in Figure 53, will mean that the reference
input sees a significant external source impedance. External
decoupling on the REFIN(+) and REFIN(–) pins would not be
recommended in this type of circuit configuration.
Reference Detect
The ADuC824 includes on-chip circuitry to detect if the part has a
valid reference for conversions or calibrations. If the voltage
between the external REFIN(+) and REFIN(–) pins goes below
0.3 V or either the REFIN(+) or REFIN(–) inputs is open circuit,
the ADuC824 detects that it no longer has a valid reference. In
this case, the NOXREF bit of the ADCSTAT SFR is set to a 1. If
the ADuC824 is performing normal conversions and the NOXREF
bit becomes active, the conversion results revert to all 1s. Therefore,
it is not necessary to continuously monitor the status of the
NOXREF bit when performing conversions. It is only necessary
to verify its status if the conversion result read from the ADC Data
Register is all 1s.
If the ADuC824 is performing either an offset or gain calibration
and the NOXREF bit becomes active, the updating of the respec-
tive calibration registers is inhibited to avoid loading incorrect
coefficients to these registers, and the appropriate ERR0 or ERR1
bits in the ADCSTAT SFR are set. If the user is concerned
about verifying that a valid reference is in place every time a cali-
bration is performed, the status of the ERR0 or ERR1 bit should
be checked at the end of the calibration cycle.
Sigma-Delta Modulator
A sigma-delta ADC generally consists of two main blocks, an
analog modulator and a digital filter. In the case of the ADuC824
ADCs, the analog modulators consist of a difference amplifier,
an integrator block, a comparator, and a feedback DAC as illus-
trated in Figure 21.
DAC
INTEGRATOR
ANALOG
INPUT
DIFFERENCE
AMP
COMPARATOR
HIGH-
FREQUENCY
BITSTREAM
TO DIGITAL
FILTER
Figure 21. Sigma-Delta Modulator Simplified Block Diagram
In operation, the analog signal sample is fed to the difference
amplifier along with the output of the feedback DAC. The differ-
ence between these two signals is integrated and fed to the
comparator. The output of the comparator provides the input to
the feedback DAC so the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital data
that represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the comparator.
This duty cycle data can be recovered as a data word using a
subsequent digital filter stage. The sampling frequency of
the modulator loop is many times higher than the bandwidth of
the input signal. The integrator in the modulator shapes the
quantization noise (which results from the analog-to-digital con-
version) so that the noise is pushed toward one-half of the
modulator frequency.
Digital Filter
The output of the sigma-delta modulator feeds directly into the
digital filter. The digital filter then band-limits the response to a
frequency significantly lower than one-half of the modulator
frequency. In this manner, the 1-bit output of the comparator
is translated into a band-limited, low noise output from the
ADuC824 ADCs.
The ADuC824 filter is a low-pass, Sinc
3 or (sinx/x)3 filter whose
primary function is to remove the quantization noise introduced
at the modulator. The cutoff frequency and decimated output data
rate of the filter are programmable via the SF (Sinc Filter) SFR
as described in Table VII.
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