參數(shù)資料
型號： ADUC824BSZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 27/68頁
文件大小： 0K
描述： IC MCU 8K FLASH ADC/DAC 52MQFP
標(biāo)準(zhǔn)包裝： 800
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 8KB（8K x 8）
程序存儲器類型： 閃存
EEPROM 大小： 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x16b，4x24b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 52-QFP
包裝： 帶卷 (TR)
REV. B
ADuC824
–33–
Table IX. Primary ADC, Typical Output RMS Noise ( V)
Typical Output RMS Noise vs. Input Range and Update Rate; Output RMS Noise in
V
SF
Data Update
Input Range
Word
Rate (Hz)
20 mV
40 mV
80 mV
160 mV
320 mV
640 mV
1.28 V
2.56 V
13
105.3
1.50
1.60
1.75
3.50
4.50
6.70
11.75
69
19.79
0.60
0.65
0.95
1.40
2.30
255
5.35
0.35
0.37
0.51
0.82
1.25
Table X. Primary ADC, Peak-to-Peak Resolution (Bits)
Peak-to-Peak Resolution vs. Input Range and Update Rate; Peak-to-Peak Resolution in Bits
SF
Data Update
Input Range
Word
Rate (Hz)
20 mV
40 mV
80 mV
160 mV
320 mV
640 mV
1.28 V
2.56 V
13
105.3
12
13
14
15
15.5
16
69
19.79
13
14
15
16
17
17.5
18
18.5
255
5.35
14
15
16
17
18
18.5
18.8
19.2
Table XI. Auxiliary ADC
Typical Output RMS Noise vs. Update Rate
*
Output RMS Noise in
V
SF
Data Update
Input Range
Word
Rate (Hz)
2.5 V
13
105.3
10.75
69
19.79
2.00
255
5.35
1.15
*ADC converting in bipolar mode.
Peak-to-Peak Resolution vs. Update Rate
1
Peak-to-Peak Resolution in Bits
SF
Data Update
Input Range
Word
Rate (Hz)
2.5 V
13
105.3
16
2
69
19.79
16
255
5.35
16
NOTES
1ADC converting in bipolar mode.
2In unipolar mode peak-to-peak resolution at 105 Hz is 15 bits.
Analog Input Channels
The primary ADC has four associated analog input pins (labelled
AIN1 to AIN4) that can be configured as two fully differential
input channels. Channel selection bits in the ADC0CON SFR
detailed in Table V allow three combinations of differential pair
selection as well as an additional shorted input option (AIN2–AIN2).
The auxiliary ADC has three external input pins (labelled AIN3
to AIN5) as well as an internal connection to the internal on-chip
temperature sensor. All inputs to the auxiliary ADC are single-
ended inputs referenced to the AGND on the part. Channel
selection bits in the ADC1CON SFR detailed previously in
Table VI allow selection of one of four inputs.
Two input multiplexers switch the selected input channel to the
on-chip buffer amplifier in the case of the primary ADC and
directly to the sigma-delta modulator input in the case of the
auxiliary ADC. When the analog input channel is switched, the
settling time of the part must elapse before a new valid word is
available from the ADC.
Primary and Auxiliary ADC Inputs
The output of the primary ADC multiplexer feeds into a high
impedance input stage of the buffer amplifier. As a result, the
primary ADC inputs can handle significant source impedances and
are tailored for direct connection to external resistive-type sensors
like strain gauges or Resistance Temperature Detectors (RTDs).
The auxiliary ADC, however, is unbuffered, resulting in higher
analog input current on the auxiliary ADC. It should be noted that
this unbuffered input path provides a dynamic load to the driving
source. Therefore, resistor/capacitor combinations on the input
pins can cause dc gain errors depending on the output impedance
of the source that is driving the ADC inputs.
Analog Input Ranges
The absolute input voltage range on the primary ADC is restricted
to between AGND + 100 mV to AVDD – 100 mV. Care must be
taken in setting up the common-mode voltage and input voltage
range so that these limits are not exceeded, otherwise there will
be a degradation in linearity performance.
PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE
Tables IX, X, and XI below show the output rms noise in
V
and output peak-to-peak resolution in bits (rounded to the
nearest 0.5 LSB) for some typical output update rates on both
the Primary and Auxiliary ADCs. The numbers are typical and
are generated at a differential input voltage of 0 V. The output
update rate is selected via the SF7–SF0 bits in the Sinc Filter
(SF) SFR. It is important to note that the peak-to-peak resolu-
tion figures represent the resolution for which there will be no
code flicker within a six-sigma limit.
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