參數(shù)資料
型號(hào): ADUC7032BSTZ-88
廠商: Analog Devices Inc
文件頁(yè)數(shù): 96/120頁(yè)
文件大小: 0K
描述: IC MCU 96K FLASH DUAL 48LQFP
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 20.48MHz
連通性: LIN,SPI,UART/USART
外圍設(shè)備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 9
程序存儲(chǔ)器容量: 96KB(48K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1.5K x 32
電壓 - 電源 (Vcc/Vdd): 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
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ADuC7032-8L
Rev. A | Page 77 of 120
TIMER3—WATCHDOG TIMER
PRESCALAR
1, 16, 256
TIMER3 IRQ
WATCHDOG RESET
16-BIT
UP/DOWN COUNTER
LOW POWER
32.768kHz
16-BIT LOAD
TIMER3
VALUE
05
98
6-
0
33
Figure 35. Timer3 Block Diagram
Timer3 has two modes of operation: normal mode and watchdog
mode. The watchdog timer is used to recover from an illegal
software state. Once enabled, it requires periodic servicing to
prevent it from forcing a reset of the processor.
Timer3 reloads the value from T3LD either when TIMER3
overflows, or immediately when T3CLRI is written.
Normal Mode
Timer3 in normal mode is identical to Timer0 in 16-bit mode
of operation, except for the clock source. The clock source is the
low power 32.768 kHz oscillator and can be scaled by a factor of
1, 16, or 256. Timer3 also features a capture facility that allows
the capture of the current timer value if the Timer2 interrupt is
enabled via IRQEN[5].
Watchdog Mode
Watchdog mode is entered by setting T3CON[5]. Timer3 decre-
ments from the timeout value present in the T3LD register until
the value reaches 0. The maximum timeout is 512 seconds, using
the maximum prescalar of 1/256 and full scale in T3LD.
User software should not configure a timeout period of less than
30 ms. This is to avoid any conflict with Flash/EE memory page
erase cycles, which require 20 ms to complete a single page
erase cycle.
If T3VAL reaches 0, a reset or an interrupt occurs, depending
on T3CON[1]. To avoid a reset or an interrupt event, any value
must be written to T3CLRI before T3VAL reaches 0. This reloads
the counter with T3LD and begins a new timeout period.
When watchdog mode is entered, T3LD and T3CON are write-
protected. These two registers cannot be modified until any
reset event resets the watchdog timer.
Timer3 is automatically halted during JTAG debug access and
recommences counting only when JTAG relinquishes control of
the ARM7 core. By default, Timer3 continues to count during
power-down. This can be disabled by setting Bit 0 in T3CON.
It is recommended that the default value be used, that is, that
the watchdog timer continue to count during power-down.
Timer3 Interface
The Timer3 interface consists of four MMRs.
T3CON is the configuration MMR described in Table 57.
T3LD and T3VAL are 16-bit registers (Bit 0 to Bit 15) that
hold 16-bit unsigned integers. T3VAL is read only.
T3CLRI is an 8-bit register. Writing any value to this register
clears the Timer3 interrupt in normal mode or resets a
new timeout period in watchdog mode.
Timer3 Load Register
Name:
T3LD
Address:
0xFFFF0360
Default Value:
0x0040
Access:
Read/write
Function:
This 16-bit MMR holds the Timer3 reload value.
Timer3 Value Register
Name:
T3VAL
Address:
0xFFFF0364
Default Value:
0x0040
Access:
Read only
Function:
This 16-bit, read-only MMR holds the current
Timer3 count value.
Timer3 Clear Register
Name:
T3CLRI
Address:
0xFFFF036C
Access:
Write only
Function:
This 8-bit, write-only MMR is written (with any
value) by user code to refresh (reload) Timer3 in watchdog
mode to prevent a watchdog timer reset event. This register
must be written with a specific value (generated by user code,
based on a polynomial equation) to refresh the watchdog timer
and prevent a watchdog reset. In normal mode, writing any
value to this MMR clears the interrupt.
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