參數(shù)資料
型號(hào)： ADUC7032BSTZ-88
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 85/120頁(yè)
文件大?。?/td> 0K
描述： IC MCU 96K FLASH DUAL 48LQFP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲(chǔ)器容量： 96KB（48K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 托盤
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ADuC7032-8L
Rev. A | Page 67 of 120
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 16 interrupt sources on the ADuC7032-8L that are
controlled by the interrupt controller. Most interrupts are
generated from the on-chip peripherals such as the ADC,
UART, and so on. The ARM7TDMI CPU core recognizes
interrupts as only one of two types: a normal interrupt request
(IRQ) and a fast interrupt request (FIQ). All the interrupts can
be masked separately.
The control and configuration of the interrupt system are
managed through nine interrupt-related registers, four
dedicated to IRQ and four dedicated to FIQ. An additional
MMR is used to select the programmed interrupt source. The
bits in each IRQ and FIQ register represent the same interrupt
source, as shown in Table 51.
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid
interrupt sources are serviced.
The interrupt generation route through the ARM7TDMI core is
shown in Figure 29.
Consider the example of Timer0, which is configured to
generate a timeout every 1 ms. After the first 1 ms timeout,
FIQSIG/IRQSIG[2] is set and can be cleared only by writing to
T0CLRI.
If Timer0 is not enabled in either IRQEN or FIQEN,
FIQSTA/IRQSTA[2] is not set and an interrupt does not occur.
If Timer0 is enabled in either IRQEN or FIQEN, then
FIQSTA/IRQSTA[2] is set and either an FIQ or an IRQ
interrupt occurs.
Note that the IRQ and FIQ interrupt bit definitions in the CPSR
control interrupt recognition by the ARM core only, not by the
peripherals. For example, if Timer2 is configured to generate an
IRQ via IRQEN, the IRQ interrupt bit is set (disabled) in the
CPSR, and the ADuC7032-8L is powered down. When an
interrupt occurs, the peripherals power up, but the ARM core
remains powered down. This is equivalent to POWCON =
0x71. The ARM core can be powered up only by a reset event if
this occurs.
Table 51. IRQ/FIQ MMRs Bit Designations
Bit
Description
Comments
0
All interrupts OR’ed (FIQ only).
1
SWI is not used in IRQEN/CLR and FIQEN/CLR.
2
Timer0.
See the Timer0—Lifetime Timer section.
3
Timer1.
See the Timer1 section.
4
Timer2 or Wake-Up Timer.
See the Timer2—Wake-Up Timer section.
5
Timer3 or Watchdog Timer.
See the Timer3—Watchdog Timer section.
6
Reserved. Should be written as 0.
7
LIN Hardware.
8
Flash/EE Interrupt.
9
PLL Lock.
10
ADC.
11
UART.
See the UART Serial Interface section.
12
SPI Master.
13
XIRQ0 (GPIO IRQ 0).
See the General-Purpose I/O section.
14
XIRQ1 (GPIO IRQ 1).
See the General-Purpose I/O section.
15
Reserved. Should be written as 0.
16
IRQ3. High voltage IRQ.
High voltage interrupt; see the High Voltage Peripheral Control Interface section
17
SPI Slave.
18
XIRQ4 (GPIO IRQ 4).
See the General-Purpose I/O section.
19
XIRQ5 (GPIO IRQ 5).
See the General-Purpose I/O section.
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ADUC7032BSTZ-88-RL 功能描述:IC MCU 96K FLASH DUAL 48LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲(chǔ)器容量:4KB（4K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND
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