參數(shù)資料
型號(hào): ADUC7032BSTZ-88
廠商: Analog Devices Inc
文件頁數(shù): 60/120頁
文件大?。?/td> 0K
描述: IC MCU 96K FLASH DUAL 48LQFP
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 20.48MHz
連通性: LIN,SPI,UART/USART
外圍設(shè)備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 9
程序存儲(chǔ)器容量: 96KB(48K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1.5K x 32
電壓 - 電源 (Vcc/Vdd): 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
ADuC7032-8L
Rev. A | Page 44 of 120
Bit
Description
4
Current Channel ADC Comparator Threshold.
Valid only if the current channel ADC comparator is enabled via the ADCCFG MMR.
Set by hardware if the absolute value of the I-ADC conversion result exceeds the value written in the ADC0TH MMR. If the ADC
threshold counter is used (ADC0TCL), this bit is set only when the specified number of I-ADC conversions equals the value in the
ADC0THV MMR.
3
Current Channel ADC Overrange Bit.
If the overrange detect function is enabled via the ADCCFG MMR, this bit is set by hardware if the I-ADC input is grossly (>30%
approximately) overranged. This bit is updated every 125 μs.
When set, this bit can only be cleared by software when ADCCFG[2] is cleared to disable the function or the ADC gain is changed
via the ADC0CON MMR.
2
Temperature Conversion Result-Ready Bit.
If the temperature channel ADC is enabled, this bit is set by hardware as soon as a valid temperature conversion result is written in
the temperature data register (ADC2DAT MMR).
Cleared by reading either ADC2DAT or ADC0DAT.
1
Voltage Conversion Result-Ready Bit.
If the voltage channel ADC is enabled, this bit is set by hardware as soon as a valid voltage conversion result is written in the
voltage data register (ADC1DAT MMR).
Cleared by reading either ADC1DAT or ADC0DAT.
0
Current Conversion Result-Ready Bit.
If the current channel ADC is enabled, this bit is set by hardware as soon as a valid current conversion result is written in the
current data register (ADC0DAT MMR).
Cleared by reading ADC0DAT.
ADC Interrupt Source Enable Register
Name:
ADCMSKI
Address:
0xFFFF0504
Default Value:
0x00
Access:
Read/write
Function:
This register allows the ADC interrupt sources to be enabled individually. The bit positions in this register are the same as the
lower eight bits in the ADCSTA MMR. If a bit is set by user code to 1, the respective interrupt is enabled. By default, all bits are set to 0,
meaning that all ADC interrupt sources are disabled.
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