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| 型號(hào)： | ADUC7032BSTZ-88 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 59/120頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 托盤(pán) |
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ADuC7032-8L
Rev. A | Page 43 of 120
ADC MMR INTERFACE
The ADC is controlled and configured via a number of MMRs
that are described in detail on the following pages.
All bits defined in the top eight MSBs (Bit 8 to Bit 15) of the
ADCSTA MMR (see Table 35) are used as flags only and do not
generate interrupts. All bits defined in the lower eight LSBs (Bit
0 to Bit 7) of this MMR are logic OR’ed to produce a single ADC
interrupt to the MCU core.
In response to an ADC interrupt, user code should interrogate
the ADCSTA MMR to determine the source of the interrupt.
Each ADC interrupt source can be individually masked via the
ADCMSKI MMR, as described in the ADC Interrupt Source
Enable Register section.
All ADC result-ready bits are cleared by a read of the ADC0DAT
MMR. If the current channel ADC is not enabled, all ADC
result-ready bits are cleared by a read of the ADC1DAT or
ADC2DAT MMRs.
To ensure that I-ADC, V-ADC, and T-ADC conversion data is
synchronous, user code should first read the ADC2DAT/
ADC1DAT MMRs and then the ADC0DAT MMR. New ADC
conversion results are not written to the ADCxDAT MMRs
unless the respective ADC result-ready bits are first cleared.
The only exception to this rule is data conversion result updates
when the ARM core is powered down. In this mode, ADCxDAT
registers always contain the most recent ADC conversion results,
even though the ready bits have not been cleared.
ADC Status Register
Name:
ADCSTA
Address:
0xFFFF0500
Default Value:
0x0000
Access:
Read only
Function:
This register holds general status information related to the mode of operation or current status of the ADuC7032-8L ADCs.
Table 35. ADCSTA MMR Bit Designations
Bit
Description
15
ADC Calibration Status.
Set automatically in hardware to indicate that an ADC calibration cycle has been completed.
Cleared after ADCMDE is written to.
14
ADC Temperature Conversion Error.
Set automatically in hardware to indicate that a temperature conversion overrange or underrange has occurred. The conversion
result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
Cleared when a valid (in-range) temperature conversion result is written to the ADC2DAT register.
13
ADC Voltage Conversion Error.
Set automatically in hardware to indicate that a voltage conversion overrange or underrange has occurred. The conversion result
is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
Cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register.
12
ADC Current Conversion Error.
Set automatically in hardware to indicate that a current conversion overrange or underrange has occurred. The conversion result is
clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
Cleared when a valid (in-range) current conversion result is written to the ADC0DAT register.
11
Not Used. Reserved for future functionality and should not be monitored by user code.
10
Not Used. Reserved for future functionality and should not be monitored by user code.
9
ADC FIFO Error Flag.
Set to 1 automatically to indicate that the FIFO has overflowed. This bit does not cause an interrupt but is latched high and can be
cleared only by disabling the FIFO or reconfiguring the ADC.
Reads 0 if the FIFO is disabled or if the FIFO has not overflowed.
8
ADC FIFO Empty Flag.
Set to 1 automatically to indicate the ADC FIFO is empty. It is a flag bit only and cannot generate an interrupt.
Reads 0 if the ADC FIFO is disabled.
7
ADC FIFO Full Flag.
Set to 1 automatically to indicate the ADC FIFO is full. Any subsequent I-ADC and V-ADC conversion results cause an overflow and
corrupt the ADC FIFO.
Cleared by disabling the FIFO or reconfiguring the ADC.
6
Accumulator Comparator Threshold Exceeded.
Indicates that the absolute value of the current channel accumulator has exceeded the programmed threshold.
Cleared by disabling the accumulator comparator function in ADCCFG[6:5] or by reconfiguring the ADC.
5
Not Used. Reserved for future functionality and should not be monitored by user code.
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| ADUC7032BSTZ-88-RL | 功能描述:IC MCU 96K FLASH DUAL 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲(chǔ)器容量:4KB（4K x 8） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱(chēng):269-4116Z8F0413SH005EG-ND |
| ADUC7032BSTZ-8L | 制造商:Analog Devices 功能描述:FLASH 96K ARM7 TRIPLE 16-BIT ADC LIN IC. - Trays |
| ADUC7032BSTZ-8L-RL | 制造商:Analog Devices 功能描述:FLASH 96K ARM7 TRIPLE 16-BIT ADC LIN IC. - Tape and Reel |
| ADUC7032BSTZ-8V | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| ADUC7032BSTZ-8V-RL | 功能描述:IC BATTERY SENSOR PREC 48-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:1,500 系列:AVR® ATtiny 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C，LIN，SPI，UART/USART，USI 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):16 程序存儲(chǔ)器容量:8KB（4K x 16） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 大小:512 x 8 RAM 容量:512 x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 11x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:帶卷 (TR) |
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