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| 型號： | ADSP-21992YBC |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 46/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CTLR 16BIT 196CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點(diǎn) |
| 接口： | SPI，SSP |
| 時(shí)鐘速率： | 150MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 128kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-BGA |
| 供應(yīng)商設(shè)備封裝： | 196-MBGA（15x15） |
| 包裝： | 托盤 |
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Rev. A
|
Page 50 of 60
|
August 2007
ADSP-21992
POWER DISSIPATION
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
Number of output pins that switch during each cycle (O)
The maximum frequency at which they can switch (f)
Their load capacitance (C)
Their voltage swing (VDD)
and is calculated by the formula below.
The load capacitance includes the package capacitance (CIN of
the processor). The switching frequency includes driving the
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2tCK). The write strobe
can switch every cycle at a frequency of 1/tCK. Select pins switch
at 1/(2tCK), but selects can switch on each cycle. For example,
estimate PEXT with the following assumptions:
A system with one bank of external data memory—
asynchronous RAM (16-bit)
One 64K
16 RAM chip is used with a load of 10 pF
Maximum peripheral speed CCLK = 80 MHz, HCLK =
80 MHz
External data memory writes occur every other cycle, a rate
of 1/(4tHCLK), with 50% of the pins switching
The bus cycle time is 80 MHz (tHCLK = 12.5 ns)
The PEXT equation is calculated for each class of pins that can
drive as shown in Table 27.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation with
the following formula.
where:
PINT is IDDINT
2.5 V, using the calculation IDDINT listed in
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
PEXT
OC
×
VDD
2
×
f
×
=
PTOTAL P
=
EXT
PINT
+
Table 27. PEXT Calculation Example
Pin Type
No. of Pins
% Switching
C
f
VDD
2
= PEXT
Address
15
50
10 pF
20 MHz
10.9 V
= 0.01635 W
MSx
1
0
10 pF
20 MHz
10.9 V
= 0.0 W
WR
1
10 pF
40 MHz
10.9 V
= 0.00436 W
Data
16
50
10 pF
20 MHz
10.9 V
= 0.01744 W
CLKOUT
1
10 pF
80 MHz
10.9 V
= 0.00872 W
= 0.04687 W
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