參數(shù)資料
型號(hào)： ADSP-21992YBC
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/60頁(yè)
文件大?。?/td> 0K
描述： IC DSP CTLR 16BIT 196CSPBGA
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： SPI，SSP
時(shí)鐘速率： 150MHz
非易失內(nèi)存： 外部
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 2.50V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 196-BGA
供應(yīng)商設(shè)備封裝： 196-MBGA（15x15）
包裝： 托盤(pán)
Rev. A
|
Page 20 of 60
|
August 2007
ADSP-21992
SPECIFICATIONS
Specifications subject to change without notice.
OPERATING CONDITIONS
Table 5. Recommended Operating Conditions—ADSP-21992BBC
Parameter
Conditions
Min
Typ
Max
Unit
VDDINT
Internal (Core) Supply Voltage
2.375
2.5
2.625
V
VDDEXT
External (I/O) Supply Voltage
3.135
3.3
3.465
V
AVDD
Analog Supply Voltage
2.375
2.5
2.625
V
CCLK
DSP Instruction Rate, Core Clock
0
150
MHz
HCLK1,
2
1 The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.
2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK 2, up to a maximum of a 75 MHz HCLK for the ADSP-21992BBC.
Peripheral Clock Rate
0
75
MHz
CLKIN3
3 In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL
circuit and the associated frequency ratio.
Input Clock Frequency
0
150
MHz
TJUNC
4
4 The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that
the power dissipation of the ADSP-21992 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.
Silicon Junction Temperature
140
C
TAMB
Ambient Operating Temperature
–40
+85
C
Table 6. Recommended Operating Conditions—ADSP-21992YBC
Parameter
Conditions
Min
Typ
Max
Unit
VDDINT
Internal (Core) Supply Voltage
2.375
2.5
2.625
V
VDDEXT
External (I/O) Supply Voltage
3.135
3.3
3.465
V
AVDD
Analog Supply Voltage
2.375
2.5
2.625
V
CCLK
DSP Instruction Rate, Core Clock
0
150
MHz
HCLK1, 2
1 The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.
2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK
2, up to a maximum of an 75 MHz HCLK for the ADSP-21992YBC.
Peripheral Clock Rate
0
75
MHz
CLKIN3
3 In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL
circuit and the associated frequency ratio.
Input Clock Frequency
0
150
MHz
TJUNC
4
4 The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that
the power dissipation of the ADSP-21992 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.
Silicon Junction Temperature
140
C
TAMB
Ambient Operating Temperature
–40
+125
C
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