參數資料
型號: ADSP-21992YBC
廠商: Analog Devices Inc
文件頁數: 25/60頁
文件大小: 0K
描述: IC DSP CTLR 16BIT 196CSPBGA
標準包裝: 1
系列: ADSP-21xx
類型: 定點
接口: SPI,SSP
時鐘速率: 150MHz
非易失內存: 外部
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 2.50V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 196-BGA
供應商設備封裝: 196-MBGA(15x15)
包裝: 托盤
ADSP-21992
Rev. A
|
Page 31 of 60
|
August 2007
Clock In and Clock Out Cycle Timing
Table 17 and Figure 7 describe clock and reset operations. Com-
binations of CLKIN and clock multipliers must not select
core/peripheral clocks in excess of 160 MHz/80 MHz for the
ADSP-21992BST, 150 MHz/75 MHz for both the
ADSP-21992BBC and ADSP-21992YBC, and 100 MHz/50 MHz
for the ADSP-21992YST, when the peripheral clock rate is one-
half the core clock rate. If the peripheral clock rate is equal to the
core clock rate, the maximum peripheral clock rate is 80 MHz
for the ADSP-21992BST, 75 MHz for ADSP-21992BBC and
ADSP-21992YBC, and 50 MHz for the ADSP-21992YST. The
peripheral clock is supplied to the CLKOUT pins.
When changing from bypass mode to PLL mode, allow 512
HCLK cycles for the PLL to stabilize.
Table 17. Clock In and Clock Out Cycle Timing
Parameter
Min
Max
Unit
Timing Requirements
tCK
CLKIN Period1, 2
10
200
ns
tCKL
CLKIN Low Pulse
4.5
ns
tCKH
CLKIN High Pulse
4.5
ns
tWRST
RESET Asserted Pulse Width Low
200tCLKOUT
ns
tMSS
MSELx/BYPASS Stable Before RESET Deasserted Setup
40
μs
tMSH
MSELx/BYPASS Stable After RESET Deasserted Hold
1000
ns
tMSD
MSELx/BYPASS Stable After RESET Asserted
200
ns
tPFD
Flag Output Disable Time After RESET Asserted
10
ns
Switching Characteristics
tCKOD
CLKOUT Delay from CLKIN
0
5.8
ns
tCKO
CLKOUT Period3
12.5
ns
1 In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN = CCLK), tCK = tCCLK.
2 In bypass mode, tCK = tCCLK.
3 CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.
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