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參數(shù)資料
| 型號： | ADSP-2196MKSTZ-160 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 144-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，SPI，SSP，UART |
| 時鐘速率： | 160MHz |
| 非易失內(nèi)存： | ROM（48 kB） |
| 芯片上RAM： | 40kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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For current information contact Analog Devices at 800/262-5643
ADSP-2196
September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
14
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Clear (= 0) the PDWN bit in the PLLCTL register
Set (= 1) the STOPALL bit in the PLLCTL register
To exit Power-Down Core/Peripherals mode, the DSP
responds to an interrupt and (after five to six cycles of
latency) resumes executing instructions with the instruction
after the IDLE.
Power-Down All Mode
When the ADSP-2196 is in Power-Down All mode, the
DSP core clock, the peripheral clock, and the PLL are all
stopped. The DSP does not retain the contents of the
instruction pipeline. The peripheral bus is stopped, so the
peripherals cannot receive data.
To enter Power-Down All mode, the DSP executes an IDLE
instruction after performing the following tasks:
Enter a power-down interrupt service routine
Check for pending interrupts and I/O service routines
Set (= 1) the PDWN bit in the PLLCTL register
To exit Power-Down Core/Peripherals mode, the DSP
responds to an interrupt and (after 500 cycles to re-stabilize
the PLL) resumes executing instructions with the instruc-
tion after the IDLE.
Clock Signals
The ADSP-2196 can be clocked by a crystal oscillator or a
buffered, shaped clock derived from an external clock oscil-
lator. If a crystal oscillator is used, the crystal should be
connected across the CLKIN and XTAL pins, with two
capacitors connected as shown in Figure 6. Capacitor
values are dependent on crystal type and should be specified
by the crystal manufacturer. A parallel-resonant, funda-
mental frequency, microprocessor-grade crystal should be
used for this configuration.
If a buffered, shaped clock is used, this external clock
connects to the DSP’s CLKIN pin. CLKIN input cannot
be halted, changed, or operated below the specified
frequency during normal operation. This clock signal
should be a TTL-compatible signal. When an external clock
is used, the XTAL input must be left unconnected.
The DSP provides a user-programmable 1
to 32
multi-
plication of the input clock, including some fractional
values, to support 128 external to internal (DSP core) clock
ratios. The MSEL6–0, BYPASS, and DF pins decide the
PLL multiplication factor at reset. At runtime, the multipli-
cation factor can be controlled in software. To support input
clocks greater that 100 MHz, the PLL uses an additional
input: the Divide Frequency (DF) pin. If the input clock is
greater than 100 MHz, DF must be high. If the input clock
is less than 100 MHz, DF must be low. The combination of
pullup and pull-down resistors in Figure 6 set up a core
clock ratio of 6:1, which produces a 150 MHz core clock
from the 25 MHz input. For other clock multiplier settings,
see the ADSP-219x/2191 DSP Hardware Reference.
The peripheral clock is supplied to the CLKOUT pin.
All on-chip peripherals for the ADSP-2196 operate at the
rate set by the peripheral clock. The peripheral clock is
either equal to the core clock rate or one-half the DSP core
clock rate. This selection is controlled by the IOSEL bit in
the PLLCTL register. The maximum core clock
is 160 MHz, and the maximum peripheral clock
is 100 MHz—the combination of the input clock and
core/peripheral clock ratios may not exceed these limits.
Reset
The RESET signal initiates a master reset of the
ADSP-2196. The RESET signal must be asserted during
the power-up sequence to assure proper initialization.
RESET during initial power-up must be held long enough
to allow the internal clock to stabilize. If RESET is activated
any time after power up, the clock does not continue to run
and requires stabilization time when recovering from reset.
The power-up sequence is defined as the total time required
for the crystal oscillator circuit to stabilize after a valid V
DD
is applied to the processor, and for the internal phase-locked
loop (PLL) to lock onto the specific crystal frequency. A
minimum of 100 s ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During
Figure 6. External Crystal Connections
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